MEMV Register File Access for Vector Processor Bandwidth
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Solution Overview
Problem
Conventional vector-processor-based devices face inefficiencies in bandwidth utilization due to unneeded vector elements and mismatched computational precision during loop processing, leading to wasted bandwidth in vector register file accesses.
Innovation Solution
Implementing multi-element multi-vector (MEMV) register file access by using a DMA controller to arrange vector elements consecutively across different memory banks of the vector register file, allowing multiple elements of multiple vectors to be read with a single access, thereby optimizing bandwidth utilization based on the number of processing elements and computational precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional vector register file access is used reading one vector at a time, then the access mechanism is simple, but bandwidth utilization is poor due to unneeded vector elements and precision mismatch
Solution Approach 1:
The vector register file is divided into multiple memory banks (first memory bank, second memory bank, etc.), allowing parallel access to different vectors simultaneously. This segmentation enables multiple vectors to be read in parallel across different banks, improving bandwidth utilization without requiring a complete redesign of the access mechanism.
Solution Approach 2:
The patent transitions from sequential vector access (one dimension) to parallel multi-vector access across multiple memory banks (adding spatial dimension). By organizing vectors across multiple banks and enabling simultaneous reads from different banks, the system achieves higher bandwidth utilization through dimensional expansion of the access architecture.
2Productivity
If multiple separate vector register file accesses are used to obtain all operands, then all required data can be retrieved, but bandwidth is wasted when number of PEs is smaller than number of vector elements
Solution Approach 1:
The system performs preliminary arrangement of vectors in memory banks based on the number of processing elements and required computational precision. By pre-organizing vectors according to PE count and precision requirements, the system ensures that subsequent parallel reads access only needed data, eliminating bandwidth waste from unneeded elements while maintaining efficient processing.
Solution Approach 2:
The patent dynamically adjusts access parameters including the number of simultaneously accessed vectors, the distribution of vectors across memory banks, and the selection of vector elements based on computational precision requirements. This parameter adaptation allows the system to optimize bandwidth utilization by reading only the necessary number of vectors and elements for the given PE configuration and precision needs.
3Power
If vector register file access width is increased to match channel width, then bandwidth capacity is maximized, but additional bandwidth is wasted when computational precision is lower than channel width
Solution Approach 1:
The system implements partial action by reading only the necessary number of vector elements and vectors required for the computational precision and PE configuration, rather than always reading maximum-width vectors. This partial read approach prevents bandwidth waste from excessive data transfer while maintaining sufficient data for processing, adapting the read width to actual needs rather than maximum capacity.
Data Source
AI summary
Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device includes a vector processor comprising multiple processing elements (PEs) communicatively coupled via a corresponding plurality of channels to a vector register file comprising a plurality of memory banks. The vector processor provides a direct memory access (DMA) controller that is configured to receive a plurality of vectors that each comprise a plurality of vector elements representing operands for processing a loop iteration. The DMA controller arranges the vectors in the vector register file such that, for each group of vectors to be accessed in parallel, vector elements for each vector are stored consecutively, but corresponding vector elements of consecutive vectors are stored in different memory banks of the vector register file. As a result, multiple elements of multiple vectors may be accessed with a single vector register file access operation.