2T Non-Volatile Memory Cell Structure for Over-Erase Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory (NVM) technologies face challenges in preventing erroneous data determination due to over erase, which results in early conduction of memory cells, and struggle to achieve low programming current and high reading current simultaneously as NVM cell sizes shrink.
Innovation Solution
A non-volatile memory design featuring a 2T memory cell structure with a semiconductor substrate, a first stacked gate, a second stacked gate, a drain region, a common source/drain region, and a source region, where the N-channel select transistor cuts off the channel to prevent over erase and allows high reading current, and the N-type doped region and heavily P-type doped region in the drain region reduce programming current by facilitating electron tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a select transistor is added at the drain side of each memory cell to prevent over erase, then erroneous data determination is prevented, but device complexity increases
Solution Approach 1:
The memory cell is segmented into two functional transistors: a memory transistor for data storage and a select transistor for channel control. This segmentation allows the select transistor to independently manage channel conduction and prevent over-erase errors without requiring additional complex circuitry, resolving the contradiction between reliability improvement and device complexity
Solution Approach 2:
The select transistor serves multiple functions: it controls channel conduction during read operations, prevents over-erase during programming, and enables low-programming current operation. By making the select transistor multi-functional, the patent avoids adding more components to achieve these functions, thus preventing increase in device complexity while maintaining reliability
2Productivity
If NVM cell size is shrunk to increase density, then productivity improves, but programming current increases and reading current decreases
Solution Approach 1:
The drain region is doped with P-type dopants to create a localized P+N junction with high electric field strength. This local quality enhancement at the drain region enables efficient electron tunneling into the floating gate during programming, allowing low-programming current operation even in scaled-down cells, thus resolving the contradiction between increased density and reduced programming current
3Productivity
If NVM cell size is shrunk to increase density, then productivity improves, but reading current decreases
Solution Approach 1:
The patent changes the doping parameters of the drain region by introducing P-type dopants to create a P+N junction. This parameter change creates a high electric field region that enhances electron tunneling efficiency, enabling strong read currents even in scaled-down memory cells, thus resolving the contradiction between increased density and maintained reading current
4Reliability
If over erase prevention is implemented using a program verify circuit, then reliability improves, but device complexity increases
Solution Approach 1:
The patent extracts the over-erase prevention function from complex program verify circuits and implements it through the inherent channel control capability of the select transistor. By taking out this function and implementing it through a simpler mechanism already present in the 2T structure, reliability is improved without increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2T memory cell structure effectively prevents erroneous data determination by cutting off the channel during over erase and allows for low programming current and high reading current, enhancing the performance of non-volatile memory.
Implementation Method 1
a first stacked gate formed on the semiconductor substrate, wherein the first stacked gate comprises a tunneling dielectric layer, a floating gate
Implementation Method 2
the drain region comprises an N-type doped region and a heavily P-type doped region formed in the N-type doped region
Data Source
AI summary
A non-volatile memory and fabrication method thereof are disclosed. The non-volatile memory includes at least one 2T memory cell. Each 2T memory cell includes a semiconductor substrate, a first stacked gate and a second stacked gate formed on the semiconductor substrate, and a drain region, a common source/drain region and a source region formed in the semiconductor substrate. The source region and the common source/drain region are both N-type doped, and the drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The 2T memory cell is capable of preventing erroneous data determination caused by over erase and has both a low programming current and a high reading current, which improves the performance of the non-volatile memory.