Solid-State Devices TRIZ Cases

A non-uniform impurity profile in the insulating layer raises breakdown voltage while lowering on-resistance in a semiconductor structure.

Rigid pillar members set the air gap in an image sensor package, avoiding bond viscosity variation and improving assembly consistency.

Concave-convex bank patterns and matched electrodes scatter emitted light to raise side luminance and light emission efficiency in displays.

Sparse pixel capture and host feedback let the sensor send only relevant image data, cutting power and bandwidth for vision tasks.

Selective dielectric deposition lets on-chip capacitors use different thicknesses for higher capacitance density across varying voltage levels.

A diffuser-filled molding layer and anti-glare stack reduce regional brightness variation in modular micro LED displays for consistent image quality.

Oxide-tolerant bonding and post-bonded electrodes ease small-pitch micro-LED alignment while improving yield, reliability, and light extraction.

Measured electrical and optical screening enables area-based pixel transfer that cuts handling time and prevents display mura.

Perpendicular pad geometry and a dummy pad prevent electrode contact during micro-semiconductor chip placement, avoiding shorts and repair steps.

Metal-filled trench isolation around SPAD pixels absorbs stray photons and uses doped liners to curb dark current for cleaner depth imaging.

A barrier layer isolates aluminum wiring from the light-shielding film in stacked image sensors, preventing shorts and stabilizing power supply.

A reference photodiode and a UV-sensitive photodiode separate 200-275 nm signals from stray visible light for more accurate low-intensity UV detection.

A controlled-index cooling medium removes heat from an LED-pumped luminescent concentrator while preserving total internal reflection.

Scanning reflected light across cell groups lets the controller bias only active avalanche photodiodes, simplifying wiring and reducing crosstalk noise.

Stacked power lines with insulating layers and overlap reduce display short-circuit risk while limiting voltage drop and light-induced transistor damage.

Staggered die stacks with external conductive links raise circuit density while improving heat dissipation and mechanical stability.

A control circuit maps control-signal states to data, command, address, and status paths, speeding memory chip operations without excessive complexity.

Alternating assembly wiring, clad layers, and stepped insulation help self-assemble micro-LEDs faster while reducing corrosion and short-circuit defects.

Field plates around isolated P-wells raise SCR breakdown voltage and ESD current handling without the footprint and resistance of stacked devices.

Integrated discharge paths and a charge reservoir protect fingerprint sensor cells from ESD while limiting parasitic capacitance and preserving sensitivity.

Electric-field self-assembly and a covalent bond layer improve micro-LED transfer accuracy while preventing diode separation on display substrates.

Valley portions partition dense pixel circuits and route signals through openings, helping foldable displays keep high resolution and impact resistance.

A photonic crystal array with tapered axial LEDs places active layers at resonance peaks to narrow the spectrum and strengthen directional emission.

Bottom-emitting micro-LED fabrication improves light extraction, preserves pixel source position, and enables color conversion for display integration.

High-opacity filler between adjacent emitters blocks light leakage, improving polarizer throughput and reducing 3D ghosting discomfort.

Placing column circuits beneath the pixel section on a second substrate limits chip area growth and reduces heat-driven dark current non-uniformity.

A chip-integrated Fresnel structure redirects and concentrates photons near the p-n junction, boosting photodetector sensitivity without lens cost.

Honeycomb lower electrodes and distinct upper support openings reduce DRAM capacitor defects and stabilize electric characteristics under varying voltages.

Through-hole-filled spacers maintain uniform cell gaps and mechanical strength while reducing pixel unevenness in high-definition LCDs.

A monolithic high-transmissivity window in the housing wall seals photonic components while blocking stray light and adjacent circuitry noise.

Alternating magnetic and non-magnetic layers improve crystal orientation and perpendicular anisotropy, boosting MRAM resistance change and lowering errors.

Stacked and folded capacitors cut parasitic coupling and charge disturbance, improving non-volatile memory retention and endurance.

A ringed electrode and enclosed photoelectric layer cut dark-state leakage current while shielding divergent light in flat panel detectors.

Selective metal plating by gate pitch forms self-aligned CTF cells and MIM capacitors, cutting lithography cost and overlay errors.

Adjacent transfer electrodes and semiconductor layers improve charge collection, reduce variation, and support finer outdoor ToF pixels.

A metal-layer aperture and surrounding via layout blocks stray light paths to active circuitry, reducing optical crosstalk in optical sensors.

Opening portions in the anode and an underlying reflector recover back-emitted micro LED light and redirect it forward to improve luminance.

By mounting the LED and driver on one surface, this package cuts cross-sectional area, simplifies bonding, and supports smaller display pixels.

A TFT-layer fingerprint module and through-hole layout improve reflected light capture, micro-LED alignment, display quality, and cost.

Recessed insulating film regions redirect stray light between adjacent chips, improving photosensitivity inspection accuracy.

Micro-LEDs driven by a TFT panel cut display power use while reflective electrodes improve light extraction and brightness uniformity.

Frontside and backside biased trench isolation suppress crosstalk and dark current while raising full well capacity and near-infrared response.

A 4×4 or 8×8 RGB-heavy pixel pattern removes clear pixels to reduce crosstalk while maintaining sensitivity, color accuracy, and resolution.

A three-electrode capacitor layout boosts capacitance in less chip area while keeping voltage coefficients low for denser IC designs.

An inclined bridging part links adjacent LED units while limiting film-layer cracks, reducing power loss and improving display brightness.

Multiple repair line sets let an array substrate reconnect several defective data lines, raising display yield without affecting the display area.

A reconfigurable interface circuit continuously tests fixed hardware functions, improving qualification and reliability under changing conditions.

Multiple inorganic passivation layers and an adhesive encapsulation stack limit moisture permeation and reduce LED defects in displays.

A recessed bond pad increases sidewall contact with metal layers to resist low-κ dielectric peeling and improve IC bonding yield.

Applying VPD to non-readout pixel electrodes shifts charges to shared readout pixels, cutting noise while preserving conversion efficiency.

A low-threshold layer between adjacent OLED color regions diverts current, reducing leakage current, color shift, and gradation errors.

Optical lenses and reflective sidewall coatings narrow micro LED beam angles and boost intensity for lower AR/VR image crosstalk.

A vertically stacked epitaxial micro LED structure enables high-resolution displays without complex chip transfer or color conversion layers.

A bridged connecting member links side-surface conductive lines to panel terminals, improving electrical contact and production yield.

Auxiliary positioning areas with opposite light transmittance improve OLED subpixel alignment and reduce inkjet printing defects.

An inorganic light-absorbing layer enables clean phosphor release during micro LED transfer, preventing re-adherence, surface deformation, and substrate damage.

Bridging terminals in panel openings improve motherboard bonding reliability and lower contact impedance in bezel-free splicing displays.

A conductorized active layer narrows TFT channels to meet high current demand while reducing self-heating and improving signal stability.

A thin α-ray blocking film in the sensor cover stack suppresses glass-induced white points while preserving light transmission and image quality.

A shared n+1 interconnect layout lets multiple LED elements be controlled individually or together while keeping the substrate wiring compact.

Buried metal arrays in dual dielectric layers tune RGB wavelength bands and bandwidth in color filters under 400 nm for smaller image sensor pixels.

A hydrosilylation-cured silicone blend limits weight loss, hardness shift, and cracking during thermal aging in optical semiconductor sealing.

Side-wall pads and RDL replace TSVs in stacked dies, cutting keep-out zones, shrinking footprint, and freeing IP core placement.

Integrated limit resistors in each GmAPD FPA pixel curb peak current into the ROIC, reducing optical overstress damage and data corruption.

Dual material stop layers correct over-etch depth so DRAM capacitor holes stay uniform and expose connecting pads at nearly the same time.

Vertical layer segmentation and isolation improve low-light sensitivity while keeping avalanche breakdown voltage low and detection uniform.

Metal bit-line discharge routing and thicker word lines cut RC delay in dual-port SRAM cells, improving read current and access speed.

A Formula 1 polymer coating improves OLED hole transport layer stability and interface quality, lowering driving voltage and extending service life.

A polarity-tuned infiltrating solution removes electron transport layer impurities without dissolving the material, improving QLED efficiency and life.

Multi-layer microlenses and lattice trenches widen the light spot to raise quantum efficiency and reduce same-color pixel sensitivity variation.

An anisotropic graphene or WTe2 interlayer boosts photocurrent while limiting dark current, improving small-signal detection in low light.

Color-gamut adjusting units align blue-emitter spectra across splicing screens to prevent abnormal seam images and improve display uniformity.

Magnetic plates and substrate layers align and transfer miniaturized LEDs accurately, reducing placement errors in display panel assembly.

Shared gate lines let multiple CMOS pairs run in phase within standard cells, cutting wiring complexity, wasted area, and layout cost.

A bridge-linked staircase connects adjacent 3D memory arrays while saving stair area and easing insulating material deposition and polishing.

Porosified and non-porosified semiconductor regions tune bandgap and offset lattice mismatch to simplify multicolor LED pixel fabrication.

Placing the touch unit in the non-pixel region cuts crosstalk and signal loss while simplifying array substrate processing.

A 2T memory cell uses a select transistor and tailored drain doping to prevent over-erase errors while keeping programming current low and read current high.

A stacked inorganic-organic pixel layout reduces F-number-dependent color sensitivity shifts and false colors in CMOS image sensors.

Oxygen-blocking insulators preserve oxide semiconductor stability during heat treatment, supporting denser low-power transistor stacks.

Insulating regions and separation trenches isolate substrate potential between GaN lateral transistors, stabilizing current collapse and gate threshold.

Different microlens heights and curvatures compensate D-cut lens aperture differences, improving autofocus accuracy across the sensor.

A dam over power wires guides organic layer spread in OLED encapsulation, improving thin film sealing quality and touch performance.

Parallel diversion and filling grooves improve molding fill, protect leads, and keep packaging material out of the photosensitive region.

Commodity FPGA chips combine NVM LUT storage, SRAM logic, and an interposer package to lower NRE cost for advanced-node logic development.

Wavelength conversion materials and current-limiting regions help micro-LED arrays improve transfer accuracy, optical inspection, and emission efficiency.

A transparent OLED transmission region also emits light, balancing transmittance, brightness, lower driving voltage, and longer panel life.

A biscarbazole and triphenylene buffer layer improves OLED luminance, lowers driving voltage, and extends lifetime through triplet energy matching.

A coplanar control layer aligns multiple micro-lens chips to a shared focal plane, improving optical performance in parallel image sensing packages.

Recessed connection electrodes link LED modules to a support substrate, reducing dark lines while enabling seamless large-area displays.

Low-power laser switching of adhesive viscosity lets mini LED chips be removed and reattached without damage, improving repair yield and display quality.

A polarizer, quarter-wave retarder, and reflective polarizer cut ambient reflections while recycling light to raise QD-OLED contrast and luminance.

Vertical stacking with dichroic filtering and light-blocking layers cuts pixel area while limiting crosstalk and preserving color purity.

A trench-separated support region concentrates current in the emitting portion, improving luminous efficiency, strength, and transfer yield.

A dual-gate LTPO panel layout lowers the electric field on oxide TFTs to limit threshold voltage drift and improve reliability.

Electric-field-driven metal films switch a backlight between collimated and scattered light, enabling privacy mode with higher light use and thinner LCD panels.

Simultaneous electrode energizing and light irradiation cuts QLED curing time by at least 50% while improving external quantum efficiency.

Grooved planarization and a flexible electrode layer create dual-channel wiring that prevents signal loss when non-display metal lines bend or crack.