3D Die Stack Side-Wall Interconnects for TSV-Free Footprint Reduction
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Solution Overview
Problem
Conventional 3D chip stacks rely on through-silicon vias (TSVs) for interconnections, leading to larger chip sizes and inefficient use of space due to keep-out zones and limitations in placing IP cores on adjacent dies.
Innovation Solution
The implementation of side wall interconnections between die layers in a semiconductor package, which includes exposing side wall pads on the die layers for bonding and using additional layers like RDL to provide vertical interconnections, reducing the need for TSVs and optimizing chip footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for interconnections between die layers, then vertical connectivity is achieved, but chip footprint increases due to keep-out zones
Solution Approach 1:
The patent transitions from vertical TSV interconnections to lateral side-wall interconnections. By moving the interconnection path from the vertical dimension (through-silicon) to the lateral dimension (side-wall), the design eliminates the need for large keep-out zones around vertical vias, thereby reducing chip footprint while maintaining connectivity.
Solution Approach 2:
Instead of creating holes through the silicon substrate from top to bottom (TSV approach), the patent inverts the approach by forming interconnections along the side-walls of the dies. This inversion of the interconnection geometry allows pads to be placed at the periphery rather than requiring central via locations, reducing the keep-out zone impact.
2Productivity
If TSVs are used for interconnections, then die stacking is enabled, but IP core placement flexibility is reduced
Solution Approach 1:
By shifting interconnections to the side-walls, the patent enables IP cores to be placed more freely on the die surface without needing to align with vertical via locations. This dimensional shift from vertical to lateral interconnection provides greater placement flexibility for IP cores while maintaining die stacking capability.
3Area of stationary object
If side wall interconnections are used, then chip footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the side-wall interconnection structures during the die fabrication process itself, before die stacking. By pre-forming the lateral interconnection paths and pads on each die, the manufacturing complexity is managed in controlled stages rather than requiring complex post-stack modifications.
Data Source
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AI summary
Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.