Multi-Chip FPGA Logic Drive Using NVM LUT Storage
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Solution Overview
Problem
The high Non-Recurring Engineering (NRE) costs and inefficiencies associated with transitioning from Field Programmable Gate Array (FPGA) IC chips to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly due to larger chip size, higher power consumption, lower performance, and increased costs as semiconductor technology nodes advance, hinder innovation and adoption of advanced semiconductor technology.
Innovation Solution
A standardized commodity logic drive utilizing multiple FPGA IC chips with non-volatile memory cells and SRAM cells, allowing for field programming and reducing NRE costs by enabling developers to implement innovations using advanced technology nodes with significantly lower expenses, similar to those of standard commodity DRAM or NAND flash memory production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the FPGA chip into distinct functional regions: non-volatile memory cell arrays for configuration storage, SRAM cells for operational logic, sense amplifiers for memory access, and programmable interconnect structures. This segmentation allows each component to be optimized independently while maintaining overall field programming capability.
Solution Approach 2:
The patent creates a universal FPGA chip design that can be programmed for multiple different applications and logic functions. The same physical chip structure serves both as non-volatile configuration storage and as operational logic fabric, eliminating the need for separate ASIC designs for different applications.
2Productivity
If advanced semiconductor technology nodes are used, then productivity and performance are improved, but manufacturing cost and NRE expenses increase
Solution Approach 1:
The patent uses standard commodity FPGA chip designs that can be replicated across multiple technology nodes without requiring expensive custom mask sets for each application. The same logical design can be copied and fabricated at different process nodes, reducing NRE costs while maintaining performance benefits of advanced nodes.
Solution Approach 2:
The patent enables the same FPGA architecture to be implemented across different semiconductor technology nodes by changing fabrication parameters rather than redesigning the logic. This allows performance optimization through node selection without incurring proportional NRE cost increases.
3Use of energy by moving object
If ASIC or COT IC chips are used for volume production, then power consumption is reduced and performance is improved, but adaptability and ease of manufacture worsen
Solution Approach 1:
The patent makes the chip dynamically reconfigurable through field programming, allowing the logic fabric to be programmed for specific applications to optimize power consumption and performance similar to ASICs, while retaining the ability to reprogram for different applications later. The non-volatile memory enables the chip to maintain its programmed state without continuous power.
Solution Approach 2:
The FPGA chip is programmed in the field by the end user or system integrator rather than requiring factory programming, allowing the same chip to be optimized for different applications based on actual usage requirements. This self-service programming capability provides ASIC-level optimization without sacrificing adaptability.
Data Source
AI summary
A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.