Standard Cell CMOS Layout With Shared Gate Lines
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Solution Overview
Problem
The existing standard cell layout in semiconductor integrated circuits faces challenges in efficiently arranging complementary transistor pairs in phase, leading to wasted space and increased costs due to complex wiring patterns and limited space for connecting gate lines, especially when trying to drive multiple CMOS pairs in phase.
Innovation Solution
The solution involves arranging standard cells with a standardized cell length and incorporating multi-height cells that share power lines, allowing for integral gate line formation to reduce the number of internal wirings and eliminate complex wiring shapes, thereby optimizing space usage and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple CMOS pairs are arranged in a standard cell to be driven in phase, then the circuit functionality is improved, but the cell area increases and wiring complexity increases due to the need to connect multiple gate lines
Solution Approach 1:
The patent merges multiple gate lines into a single common gate line that is shared by multiple CMOS pairs. This is achieved by connecting the gate electrodes of multiple CMOS pairs in parallel to the same gate line, thereby reducing the number of separate gate lines needed and decreasing the cell area while maintaining the ability to drive multiple CMOS pairs in phase.
Solution Approach 2:
The common gate line serves multiple functions by simultaneously controlling multiple CMOS pairs within the standard cell. This multi-functional gate line structure allows a single wiring element to perform the gate control function for several transistor pairs, reducing overall wiring complexity and space requirements.
2Reliability
If multiple gate lines are connected using upper layer wirings, then the gate connections are achieved, but the wiring complexity increases and manufacturing cost increases
Solution Approach 1:
The patent extracts the gate connection function from the upper layer wiring structure and implements it directly in the lower layer using a shared gate line approach. By taking out the need for complex upper layer interconnections and replacing them with a simpler common gate line structure in the lower layer, the wiring complexity and manufacturing cost are reduced while maintaining reliable gate connections.
3Area of stationary object
If the standard cell length is increased to provide more space for wiring, then the wiring space is improved, but the layout efficiency decreases and more wasted space occurs
Solution Approach 1:
The patent optimizes the wiring layout by utilizing the vertical dimension more effectively. Instead of increasing the horizontal cell length, the design arranges multiple CMOS pairs vertically along a common gate line, allowing efficient use of the available space in the standard cell without extending the cell length and maintaining high layout efficiency.
Data Source
AI summary
Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair.