Stacked Folded Capacitor Layout for Memory Charge Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional non-volatile memories, such as ferroelectric memories, suffer from charge degradation and disturbance due to the routing configuration of plate-lines relative to bit-lines and word-lines, leading to polarization decay and leakage, which affects data retention and reliability.
Innovation Solution
The implementation of a stacked and folded capacitor configuration with word-line boosting and refresh mechanisms, including wear leveling schemes and error correction, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce parasitic capacitance and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memories use standard plate-line routing configurations, then device complexity is reduced, but charge disturbance and polarization decay occur leading to poor data retention
Solution Approach 1:
The patent transitions from planar routing to three-dimensional stacked capacitor configuration, placing capacitors at different vertical levels (first level and second level) to reduce parasitic capacitance and charge disturbance while maintaining routing simplicity
Solution Approach 2:
The memory array is segmented into multiple levels with capacitors positioned at different vertical stacks, allowing independent optimization of each level's routing and reducing interference between adjacent bit lines and word lines
2Reliability
If multiple capacitors are used in memory cells, then data retention and reliability are improved, but area occupancy increases making it challenging for compact devices
Solution Approach 1:
The patent utilizes vertical stacking to place multiple capacitors in the third dimension, allowing multiple capacitors per memory cell without proportionally increasing planar area occupancy
Solution Approach 2:
Capacitors are nested in a stacked configuration where first-level capacitors and second-level capacitors are vertically integrated, sharing common structures and reducing overall area footprint
3Productivity
If plate-lines are routed close to bit-lines and word-lines, then device density is improved, but charge leakage and polarization decay increase
Solution Approach 1:
By moving capacitor routing to vertical stacks with plate-lines at different elevation levels, the patent reduces parasitic capacitance coupling between plate-lines and bit/word lines while maintaining high device density through compact vertical integration
Solution Approach 2:
The stacked capacitor structure acts as an intermediary that decouples the interaction between plate-lines and bit/word lines, reducing direct parasitic capacitance while allowing close proximity routing for high density
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.