Embedded Bond Pad Structure to Prevent Low-κ Dielectric Peeling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional bond pad structures in integrated circuits (ICs) suffer from poor bonding with low-κ dielectric materials, leading to peeling issues that result in device failure and resource wastage during manufacturing.

Innovation Solution

The development of improved bond pad structures that are buried deeper within the interconnect structure of ICs, providing a larger contact surface area and stronger bonding by being in direct contact with metal layers further from the light source, reducing the likelihood of peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If bond pads are positioned at the surface of the IC, then they are easily accessible for bonding, but they suffer from poor bonding with low-κ dielectric materials leading to peeling issues

Engineering Contradiction:
ImproveAccessibility of bond padsVSAvoidBonding reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The bond pad structure transitions from a two-dimensional surface configuration to a three-dimensional embedded structure. The bond pad is positioned within a recess in the IC surface, allowing it to be accessible from the top surface while being surrounded by dielectric material on multiple sides, thereby achieving both accessibility and improved bonding through lateral contact areas.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bond pad is nested within a recess formed in the low-κ dielectric material. This nesting structure allows the bond pad to be embedded in the dielectric while maintaining access to the surface for bonding operations, and the recess walls provide additional bonding surface area that improves adhesion.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If bond pads are buried deeper within the interconnect structure, then bonding surface area increases and peeling resistance improves, but manufacturing complexity increases

Engineering Contradiction:
ImproveBonding reliabilityVSAvoidManufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The recess structure is formed in the low-κ dielectric material before the bond pad metal is deposited. This preliminary formation of the recess geometry allows subsequent metal deposition to conformally fill the structure, automatically creating the embedded bond pad configuration without requiring additional complex processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the geometric parameters of the bond pad structure by creating a recess with specific depth and width dimensions. This parameter change transforms the bond pad from a surface-level feature to an embedded feature, increasing the effective bonding surface area while maintaining manufacturability through standard etch and deposit processes.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If conventional bond pad structures are used, then manufacturing process is simpler, but peeling occurs resulting in device failure and resource wastage

Engineering Contradiction:
ImproveManufacturing process simplicityVSAvoidBonding reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The bond pad structure employs a composite configuration combining the low-κ dielectric material and the metal bond pad in a specific architectural arrangement. The dielectric material forms both the surrounding matrix and the recess structure, while the metal bond pad fills the recess, creating a composite structure that leverages the properties of both materials to achieve improved bonding.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11894410B2Bond pad structure for bonding improvement
Publication Date: 2024.02.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11894410B2 patent drawing
  • US11894410B2 patent drawing
  • US11894410B2 patent drawing

AI summary

Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.