Self-Aligned Charge Trap Flash Cells With Selective Metal Plating
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Solution Overview
Problem
Charge trap flash (CTF) memory cells require additional patterning operations, leading to increased costs and manufacturing defects such as overlay errors, due to their complex integration with standard logic and SRAM devices.
Innovation Solution
The implementation of self-aligned CTF memory cells and metal-insulator-metal (MIM) capacitors using selective metal plating based on gate pitch, which allows for parallel fabrication with transistor devices, reducing the need for extra lithography steps and leveraging a tungsten nucleation poisoning process to achieve distinct grain sizes in electrodes, thereby eliminating overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CTF memory cells are integrated with standard logic and SRAM devices using conventional patterning methods, then functional integration is achieved, but manufacturing cost increases and overlay errors occur
Solution Approach 1:
The patent merges the patterning process for CTF memory cells with the standard logic device fabrication process by using a common mandrel structure. Both device types are formed simultaneously through selective deposition and etching steps, eliminating the need for separate lithography operations and reducing overlay errors between different device layers
2Adaptability or versatility
If additional mask and lithography steps are used to fabricate CTF memory cells, then device functionality is achieved, but manufacturing complexity and defect rate increase
Solution Approach 1:
The patent implements a self-aligned fabrication approach where the CTF memory cell structure automatically defines its own pattern boundaries through selective material deposition on existing mandrels. The process uses self-limiting deposition steps and selective etching that follow the mandrel geometry, eliminating the need for external lithography alignment steps and reducing process complexity
3Adaptability or versatility
If conventional patterning methods are used for CTF memory cells, then device integration is achieved, but overlay errors and manufacturing defects increase
Solution Approach 1:
The patent establishes precise pattern definitions early in the fabrication process by forming mandrel structures that serve as self-aligned templates for subsequent CTF memory cell formation. These preliminary mandrel structures are created using standard logic device patterning steps, ensuring that all subsequent deposition and etching operations are automatically aligned to the same reference framework, thereby eliminating overlay errors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and eliminates overlay errors, enabling cost-effective production of self-aligned CTF memory cells and MIM capacitors with enhanced microstructure characteristics, allowing for improved performance and tuning capabilities.
Implementation Method 1
leveraging a tungsten nucleation poisoning process to achieve distinct grain sizes in electrodes
Implementation Method 2
The poisoning is selectively implemented in order to completely poison the nucleation layer in the wide pitch regions of the CTF memory cells or the MIM capacitor, whereas the narrow pitch regions of the transistor devices is only partially poisoned
Implementation Method 3
selective metal plating based on gate pitch
Implementation Method 4
The partial poisoning allows for bottom-up fill of the gate electrode in the transistor devices, without deposition in the CTF memory cells or the MIM capacitor
Data Source
AI summary
Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.