3D Memory Staircase Bridge Layout for Dense Array Connection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge lies in the difficulty of scaling down planar memory cells due to limitations in process technology and fabrication techniques, leading to constraints in memory density and increased costs, which 3D memory architecture aims to address by introducing a staircase structure in memory devices to enhance storage capacity and connectivity between memory array structures.

Innovation Solution

The implementation of a 3D memory device with a staircase structure that includes a bridge structure and multiple staircases, where each stair is electrically connected to the bridge, allowing for efficient electrical connections between memory array structures and reducing the area required for forming stairs, thereby simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If planar memory cells are scaled to smaller sizes using improved process technology, then memory density increases, but fabrication becomes challenging and costly beyond a lower limit

Engineering Contradiction:

Improvememory densityVSAvoidfabrication difficulty

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from planar (2D) memory cell architecture to a three-dimensional architecture incorporating staircases and bridge structures. This dimensional change allows memory cells to be stacked vertically, dramatically increasing memory density without further reducing lateral feature sizes, thereby avoiding the fabrication challenges and costs associated with extreme planar scaling.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If a staircase structure is introduced in 3D memory devices to enhance storage capacity, then memory density increases, but the complexity of forming stairs increases

Engineering Contradiction:

Improvestorage capacityVSAvoidstaircase formation complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The staircase structure is divided into multiple discrete stairs, each formed by sequential patterning and etching steps. This segmentation allows the complex staircase formation to be broken down into manageable, repetitive unit operations, simplifying the overall fabrication process while maintaining high storage capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent forms sacrificial layers and preliminary structures before creating the final staircase geometry. These preliminary actions prepare the substrate and guide subsequent etching steps, reducing the complexity of forming the precise staircase structure by pre-establishing reference features and material layers.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If multiple staircases are formed to connect memory array structures, then electrical connectivity improves, but the area required for stair formation increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstair formation area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The staircase structures are designed to nest within the overall memory device footprint, with stairs positioned to utilize vertical space efficiently. Multiple staircases are arranged to connect memory array structures in a compact configuration, ensuring electrical connectivity while minimizing the lateral area dedicated to stair formation.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

By transitioning to three-dimensional stacking, the patent accommodates multiple staircases vertically rather than requiring them to be distributed laterally. This vertical arrangement maintains electrical connectivity between memory arrays while significantly reducing the planar area consumed by staircase structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Reliability

If insulating materials are deposited and polished over staircase structures, then electrical isolation improves, but the fabrication process complexity increases

Engineering Contradiction:

Improveelectrical isolationVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The deposition and polishing of insulating materials is performed as a periodic, repeating process across each staircase level. This systematic approach applies the same fabrication steps uniformly to multiple stairs, improving electrical isolation while managing process complexity through standardization and repetition of proven fabrication techniques.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20240032288A1Three-dimensional memory device, memory system, and methods for forming the same

Publication Date: 2024.01.25 YANGTZE MEMORY TECH CO LTD

AI summary

A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.