Memory Chip Control Circuit for Faster Command and Address Handling
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high-speed operations due to limitations in control signal management and data processing efficiency across memory cell arrays.
Innovation Solution
A semiconductor storage device with a memory chip that includes control signal pads and a control circuit, which manages data storage and retrieval based on specific control signal states, allowing for efficient data storage, output, and status reporting through a memory cell array with a peripheral circuit and registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional control signal management is used in semiconductor storage devices, then device structure remains simple, but operation speed is limited
Solution Approach 1:
The control circuit is divided into multiple functional units including a first control unit that receives and processes the first control signal, a second control unit that receives and processes the second control signal, and a data processing unit. This segmentation allows parallel processing of control signals and data, enabling high-speed operations while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The control circuit performs preliminary processing of control signals before data operations. The first control unit prepares control signals for row operations, while the second control unit prepares control signals for column operations, allowing the memory system to be pre-configured for upcoming data access patterns, thereby increasing operation speed.
2Productivity
If data processing efficiency is improved through enhanced control circuits, then operation speed increases, but device complexity increases
Solution Approach 1:
The control circuit is designed with multi-functional units that can handle multiple operations. The first control unit manages row selection and word line control, while the second control unit manages column selection and bit line control. These units can be configured for different operations (read, write, erase) without requiring separate dedicated circuits, thus improving data processing efficiency while controlling complexity through universal design.
Solution Approach 2:
The control circuit employs dynamic signal routing and configurable control paths. Control signals are dynamically directed to appropriate memory blocks based on operation requirements, and the control units can switch between different operational modes (read/write/erase) by reconfiguring their internal logic, enabling high productivity without permanent complex hardware for each function.
Data Source
AI summary
A semiconductor storage device comprises a memory chip including first and second control signal pads to which first and second control signals are to be input, respectively, a data signal pad to and from which a data signal is to be input and output, and a control circuit. The control circuit stores data in the data signal in a data register, when the first and second control signals are at a first state, stores data in the data signal in a command register, when the first control signal is at a second state and the second control signal is at the first state, stores data in the data signal in an address register, when the first control signal is at the first state and the second control signal is at the second state, and outputs status data when the first and second control signals are at the second state.