2T Memory Cell Layout With Source-Drain Coupling for Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies face challenges in achieving high density and low power consumption while maintaining efficient operation, particularly in system-on-a-chip (SoC) technology, where existing memory cells do not effectively leverage the benefits of low-temperature operation for extended memory storage.
Innovation Solution
The implementation of 2T memory cells with source-drain coupling in one transistor, utilizing angled transistors and advanced semiconductor materials, allows for increased density, reduced standby power, and improved scalability by optimizing transistors for low-temperature operation, which reduces leakage and enhances memory storage duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell configurations are used, then manufacturing and design are straightforward, but memory cell density is limited and transistor footprint is large
Solution Approach 1:
The patent merges the source and drain terminals of one transistor with the source and drain terminals of another transistor, creating a shared source-drain structure. This merging reduces the total number of discrete terminals and interconnections required, thereby increasing memory cell density while managing design complexity through systematic terminal sharing across the two-transistor configuration
Solution Approach 2:
The patent employs angled transistors that are rotated relative to each other, utilizing spatial orientation in a new dimension. By arranging transistors at angles rather than in conventional parallel or series configurations, the design achieves higher density packing and improved scalability without proportionally increasing layout complexity
2Loss of energy
If conventional transistor configurations are used, then design is simple, but standby power consumption is high especially at low temperatures
Solution Approach 1:
The patent optimizes the electrical parameters of the two-transistor configuration, specifically the coupling between source-drain terminals and the gating mechanisms, to reduce leakage current. By adjusting these electrical parameters and the interaction between transistors, standby power consumption is reduced while maintaining adequate memory state retention through controlled charge storage in the coupled structure
3Quantity of substance
If memory cell density is increased, then more memory can be integrated, but drive current may be reduced
Solution Approach 1:
The patent employs dynamic control mechanisms where the gating of one transistor modulates the conductance of the shared source-drain path. This dynamic interaction allows the coupled transistor structure to maintain sufficient drive current for read/write operations while occupying less space, as the active control region is shared between both transistors rather than requiring separate conduction paths
Data Source
AI summary
IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.