2T Vertical Memory Cell With Shared Access Line
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, and they often require multiple access lines and data lines for operations, which complicates the structure and power dissipation.
Innovation Solution
The memory device employs a 2T memory cell structure with a charge storage structure and a cross-point gain cell configuration, using a single access line and data line for operations, and is formed vertically with multiple levels of memory cells to achieve a smaller footprint and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional memory cell structures are used, then fabrication constraints and physical limitations prevent further size reduction, but the patent employs a 2T vertical memory cell structure to overcome these limitations and achieve smaller cell dimensions
Solution Approach 1:
The patent transitions from planar memory cell structures to a vertical three-dimensional configuration. The 2T memory cell is constructed with stacked components extending in the vertical dimension, allowing continued scaling of memory cell size despite reaching physical limitations of conventional planar fabrication approaches.
2Reliability
If multiple access lines and data lines are used for memory operations, then complete memory cell access is achieved, but the structure becomes complicated and power dissipation increases
Solution Approach 1:
The patent combines multiple access lines into a single shared access line that controls both transistors in the 2T memory cell. This merging of access lines reduces the total number of interconnects required, simplifying the overall device structure and reducing power dissipation while maintaining complete memory cell access capability through coordinated transistor control.
3Reliability
If multiple access lines and data lines are used, then full memory control is achieved, but power dissipation increases
Solution Approach 1:
The patent merges multiple access lines into a single shared access line configuration. This reduction in the number of active conductors directly decreases resistive power losses while the vertical 2T structure optimizes current paths to minimize energy dissipation during read and write operations.
Solution Approach 2:
The single access line in the patent serves multiple functions: it controls both transistors in the memory cell, enables both read and write operations, and provides selective access to different memory cells. This multi-functionality reduces the total number of dedicated lines required, thereby reducing overall power dissipation.
4Quantity of substance
If conventional memory cell structures are used, then current technology is maintained, but storage density cannot be increased further due to physical limitations
Solution Approach 1:
The patent utilizes vertical stacking to increase storage density. By constructing memory cells in three dimensions rather than maintaining planar two-dimensional structures, the design achieves higher storage density within the same footprint area, effectively increasing the quantity of stored information without further reducing lateral dimensions.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.