Digital Storage TRIZ Cases

Stress-induced phase transitions in functional oxide heterostructures enable multi-stage resistance switching.

Storing fuse data in the memory cell array repairs defective cells and trims internal voltages without additional processing steps.

Virtual power supply circuit drives bitlines to opposite logic states, enabling fast array reset while reducing current sinking requirements.

A memory controller converts insignificant data bits into parity bits to generate second data for transmission.

Cooling the wafer to 60 K during pinned layer deposition improves thermal stability against high-temperature processing.

Main word line driving circuit switches supply voltage to bias levels using level shifters and a multiplexer.

Intermittent DLL activation during self-refresh reduces command issuance delay while maintaining power efficiency.

Dual programming scheme manages reclaimed flash memory blocks using UECC and CECC lists to maintain data integrity.

Segmenting memory units allows grouped source drivers to apply local voltage levels, suppressing bit line leakage while maintaining storage capacity.

Control circuit transmits staggered enable signals to power supply circuits, preventing surge currents from pulling down external input voltages.

Output control signal generator synchronizes data output with external clock signals to stabilize latency operations.

Prevention transistor bridges external and internal power transitions, eliminating VDL dead band disruptions that increase access times.

A refresh manager writes protective data to adjacent word lines during memory operations.

A semiconductor device segments its power supply architecture to generate an internal buck voltage for logic circuits while driving memory macros with external voltage.

A memory control circuit adjusts data acquisition timing dynamically to maintain stable signal integrity across varying fabrication conditions.

Localized gate widths and threshold voltages in selection transistors prevent damage to near memory cells during read operations.

Boost and recycling circuits lower bit line voltage below ground to overcome transistor threshold variations during low-voltage write operations.

A neural mosaic logic unit routes inputs to stacked crossbar arrays via a control circuit for efficient analog computation.

A bias circuit fixes the reference bitline voltage during readout to enhance signal margin in ferroelectric memory arrays.

Dual strap portions connect a magnetic tunnel junction to selection transistors, enabling independent heating and field currents to reduce power density.

A cascaded ferroelectric field effect transistor structure couples n-type and p-type devices in parallel to enable one-operation data retrieval.

A magnetic memory element uses a thermally unstable reference layer to enable unidirectional writing with external fields.

A memory bitcell uses a gating transistor to decouple the power supply during write operations.

A 2-transistor vertical memory cell structure uses a shared conductive line to control both transistors for compact storage.

A semiconductor memory write driver applies distinct voltages to bit and source lines based on data values.

Fine-grained negative wordline scheme applies dynamic voltage control to reduce passgate leakage while preventing overvoltage stress during standby mode.

Matrix Space architecture resolves transformation complexity by enabling concurrent row and column access for efficient parallel computations.

Parallel NMOS switches dynamically adjust the sensing range to resolve power consumption and reliability trade-offs in low-voltage memory circuits.

A sense amplifier control circuit adjusts power voltage based on external levels to stabilize operation.

A pre-read scan technique applies multiple read voltages to identify an optimal demarcation bias voltage for memory array data retrieval.

A hybrid memory circuit integrates phase change and filament switching elements across distinct vertical levels to combine data retention with low programming current.

Global bit lines connect sub-blocks to shared sense amplifiers, reducing area consumption and driver count.

Sensing circuitry performs in-place inversion inside the memory array, eliminating row line activation and reducing power consumption.

Wrapping the variable resistance layer around a columnar electrode increases conductive filament density, resolving insufficient low resistance state current.

A storage circuit customizes reference signals for each sense amplifier to accurately determine data stored in variable-resistance memory cells.

Twisted wordline strap cells route metal layers to gate structures, lowering parasitic resistance without expanding bitcell area.

Alternating line usage for odd and even column commands doubles timing margin while keeping the number of lines constant.

A laser shot breaks down the insulating material in a resistive memory cell, avoiding high forming voltages that damage neighboring components.

A read-before-programming method adjusts phase change memory cell resistance states using controller feedback.

First memory rank transmits training data and strobe signals directly to a second rank, bypassing the data buffer.

Dynamic ground adjustment reduces stress voltage on write drivers during negative bit line operations, extending device lifespan without affecting speed.

A dynamic latch circuit uses clocked transistors to store data without continuous feedback power.

Sequentially activating on-die termination circuits prevents simultaneous current spikes, stabilizing power supply voltage and reducing peak current load.

A semiconductor integrated circuit generates separate odd and even order strobe signals to control data latching timing within memory blocks.

A semiconductor storage device uses a switch unit to select between internal resistance element generation and external reference potential supply.

A power control circuit selectively switches between fixed voltage rails to enable dynamic voltage and frequency scaling in memory devices.

A memory controller adjusts drive strength via registers to optimize signal integrity across varying channel configurations.

Grouping information bits into multiple groups and employing a per-group delay line architecture to minimize skew between groups.

A data line sense amplifier uses a pre-charging unit to generate a pre-charge voltage via voltage division of power source and ground lines.