Memory Device Parallel Odd Even Column Access
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Solution Overview
Problem
Conventional memory devices face challenges in maintaining a sufficient timing margin for transmitting command/address signals to bank groups while minimizing the number of lines required, leading to increased circuit area as the number of bank groups increases.
Innovation Solution
The memory device employs a column signal transmission unit that alternates the use of first and second lines for transmitting column command and address signals based on odd-numbered or even-numbered column commands, and includes an additional column signal generation unit to generate delayed signals in specific modes, ensuring sufficient timing margin and minimizing the number of lines needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate lines are provided for each bank group to transmit command signals and column address signals, then the timing margin is increased, but the number of lines and circuit area significantly increase
Solution Approach 1:
The patent merges the transmission lines for odd-numbered and even-numbered column commands by having both types of commands share the same physical lines (BUS0:7>). The column signal transmission unit multiplexes the line usage based on the command type, thereby reducing the total number of lines required while maintaining sufficient timing margin for each command type.
Solution Approach 2:
The patent implements dynamic line allocation where the column signal transmission unit selectively assigns lines based on whether the column command is odd-numbered or even-numbered. This dynamic switching allows the same physical lines to serve different functional purposes at different times, optimizing resource utilization and reducing overall line count.
2Speed
If the operating frequency is increased to improve speed, then the timing margin reduces due to shortened clock cycle
Solution Approach 1:
The patent segments column commands into odd-numbered and even-numbered categories, allowing them to be transmitted and processed separately through the same physical lines. This segmentation enables independent timing control for each command type, ensuring that each maintains adequate timing margin even at high operating frequencies where the overall clock cycle is shortened.
Data Source
AI summary
A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.