Semiconductor Data Latch Control Circuit for Memory Bank Timing
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in efficiently managing data access and control signals between up and down memory banks, leading to potential errors in data read operations due to improper timing of control signals.
Innovation Solution
The semiconductor integrated circuit employs a control circuit that generates separate odd and even order strobe signals for accessing memory regions, using a signal processing unit to control the timing of these signals and a control signal generation unit to produce a control signal by combining them, preventing signal overlap and ensuring proper timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate odd and even order strobe signals are generated for accessing memory regions, then data latching accuracy is improved, but control circuit complexity increases
Solution Approach 1:
The patent divides the memory block into a first region and a second region, and generates separate odd-order and even-order strobe signals for each region. This segmentation allows independent control of data latching timing for different memory regions, improving data latching accuracy while managing circuit complexity through structured signal separation.
2Productivity
If consecutive accesses to up and down memory banks are performed, then productivity is improved, but timing control reliability deteriorates due to signal overlap
Solution Approach 1:
The patent employs periodic odd-order and even-order strobe signals that alternate in a structured sequence for consecutive memory bank accesses. This periodic signal generation ensures that timing control reliability is maintained during high-speed operations by preventing signal overlap while enabling continuous productivity improvement through sequential access patterns.
3Device complexity
If a single control signal is used for both up and down banks, then device complexity is reduced, but data read operation reliability deteriorates
Solution Approach 1:
The patent segments the control signal into separate odd-order and even-order strobe signals that are selectively applied to the first and second memory regions. This segmentation improves data read operation reliability by ensuring proper timing control for each region while maintaining relatively simple device complexity through systematic signal generation and selection mechanisms.
Data Source
AI summary
A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.