SRAM Array Reset via Virtual Power Supply and Bitline Driving
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Solution Overview
Problem
Existing SRAM technologies face challenges in performing fast resets and content corruptions across multiple memory cells within a single clock cycle, while also reducing power consumption and current sinking requirements.
Innovation Solution
The implementation of a virtual power supply circuit that generates a virtual power supply voltage and a memory array powered between this virtual voltage and a reference voltage, along with column driving circuitry that drives bit lines and complementary bit lines to opposite logic states in response to an internal clock signal and a latched reset signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write operations are used to reset memory cells, then each word can be reset, but it requires one clock cycle per word resulting in slow reset speed for large blocks
Solution Approach 1:
The patent merges multiple write operations into a single simultaneous operation by activating multiple word lines at once. The circuit combines the functionality of selecting and writing to multiple words across different rows in one clock cycle, thereby achieving fast reset of large memory blocks without requiring sequential operations.
Solution Approach 2:
The circuit design enables the same write driver circuitry to serve multiple word lines simultaneously through shared control logic. The universal reset mechanism can target any combination of rows and columns, providing multi-functional capability that adapts to different reset scenarios without requiring dedicated circuits for each word.
2Productivity
If multiple word lines are activated simultaneously to reset large blocks, then reset speed improves, but power consumption and current sinking requirements increase
Solution Approach 1:
The patent segments the memory array into multiple independently controllable blocks, each with its own write driver. This segmentation allows the system to activate only the specific segments that need resetting rather than the entire array, thereby reducing the total current sinking requirement while maintaining fast reset speed for the targeted portions.
Solution Approach 2:
The circuit implements partial action by allowing selective resetting of only the necessary rows and columns rather than forcing a complete array reset. The control logic enables the user to specify exactly which portions of memory need resetting, applying power and current only where needed, thus avoiding excessive current consumption.
3Productivity
If fast reset of multiple words is implemented, then productivity improves, but device complexity increases due to additional control circuitry
Solution Approach 1:
The control circuitry is designed with universal functionality that handles both conventional sequential write operations and parallel fast reset operations using the same hardware resources. The multi-functional control logic can interpret different control signals to achieve different operations, reducing the need for separate dedicated circuits for each operation type.
Solution Approach 2:
The circuit employs dynamic control signals that can be configured at runtime to enable or disable parallel operation modes. The control logic adapts its behavior based on the reset requirements, switching between sequential and parallel operation modes as needed, thereby managing complexity through dynamic reconfiguration rather than static hardware multiplication.
Data Source
AI summary
A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.