Cascaded FeFET Structure for Parallel Decision Tree Readout
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Solution Overview
Problem
Decision tree structures in machine learning require serial read operations, which can be time-consuming and resource-intensive, limiting their efficiency in processing and storage of information.
Innovation Solution
A cascading structure of non-volatile memory using n-type and p-type ferroelectric field effect transistors (FeFETs) is implemented, allowing for parallel readout of serial computations by electrically coupling the sources and top electrodes of the FeFETs in a cascaded configuration, enabling efficient storage and retrieval of information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial read operations are used for decision tree structures, then information can be read sequentially, but processing time increases and resource utilization increases
Solution Approach 1:
The decision tree is segmented into multiple levels, with each level containing multiple FeFET units that can be read in parallel. This segmentation allows the serial decision tree structure to be divided into parallel readable components, enabling simultaneous evaluation of multiple decision nodes.
Solution Approach 2:
The patent transitions from a single-dimensional serial read operation to a multi-dimensional parallel read operation by introducing additional circuitry that enables simultaneous access to multiple FeFET units across different levels of the decision tree, effectively adding a time dimension to the read operations.
2Productivity
If parallel readout is implemented for decision trees, then processing efficiency improves, but device complexity increases
Solution Approach 1:
The FeFET units are designed with universal functionality, where each unit can serve multiple purposes: storing decision tree information, enabling parallel readout, and maintaining non-volatile memory functionality. This multi-functionality reduces the need for separate dedicated components for each function.
Solution Approach 2:
The patent employs a nested structure where multiple FeFET units are organized in hierarchical levels, with each level containing units that can be read in parallel. This nesting allows the complex parallel readout functionality to be achieved through a systematic organization of simpler units.
3Reliability
If non-volatile memory is used to preserve information, then data retention improves, but energy consumption during operation increases
Solution Approach 1:
The FeFET units leverage the inherent non-volatile memory特性 of ferroelectric materials to automatically retain information without requiring continuous power supply or additional retention circuitry. The ferroelectric material maintains its polarization state naturally, providing self-service information retention.
Solution Approach 2:
The patent utilizes changes in the polarization state of ferroelectric materials to represent and retain information. By manipulating the polarization parameter of the ferroelectric layer, the system achieves non-volatile memory functionality that preserves data without continuous energy input.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cascaded FeFET structure enables one-operation parallel readout of decision trees, preserving information even when power is turned off, thus enhancing processing efficiency and reducing resource utilization.
Implementation Method 1
Permanent electrical field polarization in the ferroelectric causes this type of device to retain the transistor's state (on or off) in the absence of any electrical bias
Implementation Method 2
applying coercive voltages to selective ones of the unit structures to affect respective polarities of ferroelectric layers
Implementation Method 3
a first FeFET having a source, a drain, and a gate electrically interposed between the source and the drain
Data Source
AI summary
A unit structure of non-volatile memory is provided. The unit structure includes a substrate, an n-type ferroelectric field effect transistor (FeFET) and a p-type FeFET disposed on the substrate, first circuitry by which sources of the n-type FeFET and the p-type FeFET are electrically coupled in parallel downstream from a common terminal and second circuitry by which top electrodes of the n-type FeFET and the p-type FeFET are electrically coupled in parallel upstream of a common terminal.