Memory Bitcell Write Margin via Dynamic Power Gating
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Solution Overview
Problem
Newer memory generations using lower supply voltage degrade bitcell performance due to reduced write margin, necessitating a solution to maintain write margin while minimizing power consumption.
Innovation Solution
The implementation of a memory design with cross-coupled inverters, gating transistors, and pass transistors that decouple power supply during write operations, allowing for improved write margin without increasing power consumption by disconnecting p-MOS pull-up transistors from the VDD voltage terminal during writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a lower supply voltage is used to reduce power consumption, then power consumption is reduced, but the write margin of bitcells degrades
Solution Approach 1:
The patent applies dynamics by making the power supply connection dynamic rather than static. A gating transistor is introduced to dynamically control the connection between the p-MOS pull-up transistor and the VDD voltage terminal. During write operations, the gating transistor disconnects the power supply, while during read operations and standby modes, the power supply remains connected. This dynamic switching enables the system to achieve low power consumption during writes while maintaining adequate write margin through the controlled disconnection of the power supply.
Solution Approach 2:
The patent applies parameter changes by modifying the power supply voltage parameter dynamically. By using a gating transistor to control the connection to VDD, the effective power supply voltage to the bitcell changes between connected (VDD) and disconnected (0V) states. This parameter change allows the system to operate with lower effective power during write operations, improving write margin while maintaining acceptable power consumption levels overall.
2Reliability
If a higher supply voltage is used to maintain write margin, then write margin is maintained, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing time-based control of the power supply connection through the gating transistor. The gating transistor is activated during write operations to disconnect power, and deactivated during read operations and standby periods to maintain power connection. This periodic switching of the power supply connection allows the system to maintain write margin during critical write operations while reducing overall power consumption during less critical periods.
3Reliability
If p-MOS pull-up transistors are disconnected from VDD during write operations, then write margin is improved, but circuit complexity increases
Solution Approach 1:
The patent applies the taking out principle by extracting the power supply connection control function from the standard bitcell structure. Instead of having a direct, permanent connection from the p-MOS pull-up transistor to VDD, the patent extracts this connection and inserts a gating transistor in between. This extracted control function allows independent management of the power supply connection, enabling write margin improvement through disconnection while keeping the added complexity localized and manageable.
Solution Approach 2:
The patent applies the intermediary principle by introducing a gating transistor as a mediator between the p-MOS pull-up transistor and the VDD voltage terminal. This intermediary component provides controlled access to the power supply, allowing the system to maintain write margin by blocking power during write operations while preserving the ability to restore power during read and standby operations. The gating transistor acts as a controlled intermediary that manages the power flow based on operational mode.
Data Source
AI summary
A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.