Ferroelectric Memory Bitline Voltage Control Circuit
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Solution Overview
Problem
In ferroelectric memory devices with a folded bitline structure, the voltage variation on one bitline is influenced by the adjacent bitline, leading to a large variation in readout voltage, which can result in a decreased signal difference between '1' and '0' data, making data discrimination difficult.
Innovation Solution
A circuit configuration that includes a bias circuit to fix the voltage of the reference bitline at a high level during readout, then reset it to ground before setting it to a reference voltage, enhancing the voltage difference and signal margin by using interbitline capacitive coupling for 'overdrive' operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a folded bitline structure is used in ferroelectric memory, then the memory can operate with standard readout procedures, but the voltage of one bitline varies due to coupling with adjacent bitlines, causing large variation in readout voltage and reduced signal difference
Solution Approach 1:
The patent applies preliminary action by fixing the voltage of the non-selected bitline to a first power supply voltage (e.g., VDD) before the readout operation begins. This pre-fixing of voltage prevents the coupling effect from causing excessive voltage variation during the readout process, thereby maintaining sufficient signal difference between readout signals for reliable data discrimination.
Solution Approach 2:
The patent changes the voltage parameter of the non-selected bitline dynamically during different operation phases. During readout, the non-selected bitline voltage is fixed to VDD to minimize coupling effects. During write operations, the voltage is changed to appropriate levels for write functionality. This parameter change resolves the contradiction by optimizing the voltage state for reliable readout while maintaining write capability.
2Reliability
If the voltage of the non-selected bitline is fixed to a power supply voltage during readout, then the signal difference between readout signals is improved, but additional control circuits are required to manage the voltage fixing and resetting operations
Solution Approach 1:
The patent makes the bitline serve multiple functions: during readout operations, the non-selected bitline is fixed to VDD to provide a stable reference and improve signal difference; during write operations, the same bitline can be driven to appropriate voltage levels for write functionality. This multi-functionality reduces the need for completely separate circuits, thereby limiting the increase in device complexity while achieving improved reliability.
Solution Approach 2:
The patent introduces control circuits that act as intermediaries to manage the voltage state of bitlines. These control circuits coordinate the voltage fixing during readout and voltage resetting between operations, enabling reliable readout signals while maintaining systematic control over the bitline voltage states throughout different operation phases.
3Reliability
If additional capacitors are added to compensate for voltage variation, then the signal margin is improved, but the chip area increases
Solution Approach 1:
Instead of adding physical capacitors to compensate for voltage variation, the patent changes the voltage parameter of the non-selected bitline to VDD during readout operations. This parameter change creates a stable voltage reference that naturally improves the signal margin without requiring additional capacitive elements, thereby achieving improved reliability without increasing chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the signal difference between '1' and '0' readout signals, improving data discrimination and readout operation margins without requiring additional capacitors, thus enhancing the memory's performance and reducing chip area.
Implementation Method 1
enhancing the voltage difference and signal margin by using interbitline capacitive coupling for 'overdrive' operations
Data Source
AI summary
One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and then set the second bitline to a second power-supply voltage different from the first power-supply voltage; a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.