On-Die Termination Circuit Sequential Activation for Power Stability
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Solution Overview
Problem
The simultaneous activation of multiple on-die termination circuits in semiconductor memory devices leads to instability in power supply voltage and increased peak current, causing load on the power supply circuit, which affects the efficiency of data exchange between the controller chip and memory chip.
Innovation Solution
Implementing a control circuit that activates multiple on-die termination circuits sequentially at different timings, using a configuration of pull-up and pull-down elements driven by CMOS inverters, to prevent simultaneous activation and manage impedance matching between the memory controller and memory chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple on-die termination circuits are activated simultaneously to optimize waveform and speed up interface, then data exchange efficiency is improved, but power supply voltage stability deteriorates and peak current increases
Solution Approach 1:
The control circuit activates on-die termination circuits in advance but sequentially rather than simultaneously. The controller chip sends activation signals that trigger the termination circuits to become active before data transmission begins, but with staggered timing to avoid simultaneous activation. This preliminary activation ensures the termination circuits are ready to optimize waveform when needed, while the sequential timing prevents power supply instability and peak current issues.
2Speed
If multiple on-die termination circuits are activated simultaneously to optimize waveform, then interface speed is improved, but peak current increases
Solution Approach 1:
The control circuit implements periodic or sequential activation of on-die termination circuits rather than continuous simultaneous activation. Each termination circuit is activated in turn based on timing signals from the control circuit, creating a periodic pattern of activation that maintains interface speed optimization while distributing current draw over time. This periodic action prevents dangerous peak current spikes that would occur with simultaneous activation.
3Productivity
If multiple on-die termination circuits are activated simultaneously to optimize waveform, then data exchange efficiency is improved, but device complexity increases
Solution Approach 1:
The on-die termination circuits are designed to activate automatically in response to control signals without requiring complex external control logic. Each termination circuit contains its own control mechanism that responds to timing signals from the controller chip, enabling self-service operation. This approach maintains data exchange efficiency while avoiding the need for highly complex control circuits, as the termination circuits largely manage their own activation and operation.
Data Source
AI summary
A semiconductor memory device comprises: a plurality of on-die termination circuits connected to each of a plurality of input/output pads; and a control circuit for controlling the on-die termination circuit. The on-die termination circuit comprises: a pull-up element connected between a first terminal and an output terminal; and a pull-down element connected between the output terminal and a second terminal. The pull-up element is driven by a first pull-up element driver, and the pull-down element is driven by a first pull-down element driver. The control circuit activates a plurality of the on-die termination circuits at different timings.


