3D DRAM Vertical Bit Lines Global Interconnects
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Solution Overview
Problem
Current 3D DRAM technologies face challenges in reducing memory cell area, increasing memory cell density, and achieving higher aspect ratios, particularly due to size discrepancies between bit line pitch and bit line sense amplifiers, and issues with the placement and connection of sense amplifiers and word line drivers.
Innovation Solution
The proposed solution involves a 3D DRAM architecture with vertical bit lines, where global bit lines connect to bit lines in sub-blocks, reducing area consumption and parasitic bit line loading. This architecture also includes a reduced number of word line drivers and sense amplifiers, achieved through shared drivers and selectors, and optimized connections between memory cells and core circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D DRAM architecture is used with individual memory bit cells organized into memory cell array, then memory cell density can be increased, but area consumption increases due to size discrepancy between bit line pitch and bit line sense amplifier
Solution Approach 1:
Multiple bit lines from different sub-blocks are merged and connected to a single global bit line, which then connects to a single sense amplifier. This merging approach allows multiple bit lines to share common routing resources and sense amplifiers, significantly reducing the total area required for sense amplifier placement while maintaining high memory cell density.
Solution Approach 2:
The patent transitions from 2D DRAM architecture to 3D DRAM architecture by stacking multiple planes vertically. This dimensional change allows bit lines to extend in the vertical direction (first axis) while sense amplifiers are placed in the horizontal plane, effectively separating the routing dimension from the sensing dimension and reducing area consumption.
2Ease of operation
If one bit line is connected to one bit line sense amplifier in 2D DRAM, then bit line sensing is simplified, but area consumption increases due to equal number of BLSAs and bit lines
Solution Approach 1:
Multiple bit lines are merged into global bit lines that are then connected to shared sense amplifiers. Specifically, bit lines from multiple sub-blocks are combined onto fewer global bit lines, reducing the number of sense amplifiers needed from N (one per bit line) to M (one per global bit line, where M < N).
Solution Approach 2:
Each sense amplifier serves multiple bit lines through the global bit line intermediary, making the sense amplifier a universal component that performs sensing functions for multiple memory sub-blocks rather than being dedicated to a single bit line.
3Area of stationary object
If 3D DRAM architecture with vertical bit lines is implemented, then area consumption is reduced and routing is relaxed, but device complexity increases due to multi-plane organization
Solution Approach 1:
The memory array is segmented into multiple planes stacked vertically, with each plane containing memory cells organized in rows and columns. This segmentation allows independent addressing and sensing of each plane while sharing common bit line infrastructure, reducing overall area consumption.
Solution Approach 2:
Global bit lines serve as intermediaries between the vertical bit lines extending through multiple planes and the sense amplifiers located in the horizontal plane. This intermediary structure simplifies the connection architecture by providing a standardized interface between vertical and horizontal routing domains.
4Area of moving object
If bit line pitch is reduced for advanced DRAM technology, then memory cell size is reduced, but sense amplifier placement becomes more difficult due to larger BLSA area
Solution Approach 1:
The patent resolves the placement conflict by moving sense amplifier placement to the horizontal plane while bit lines extend vertically through multiple planes. This dimensional separation allows bit line pitch to be minimized in the horizontal direction for higher density while sense amplifiers are placed in the vertical dimension where space is abundant.
Solution Approach 2:
Multiple bit lines are merged into global bit lines that route to shared sense amplifiers located in the horizontal plane. This merging reduces the number of sense amplifier instances needed, thereby reducing total sense amplifier area and easing placement constraints despite reduced bit line pitch.
Data Source
AI summary
A 3D DRAM includes vertical bit lines. The DRAM includes a block with a 3D array of memory cells. The block includes planes stacked along a first axis. Each plane includes a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis, and columns extending along a third axis perpendicular to the first axis and the second axis. The block is divided into sub-blocks arranged along the second axis, each sub-block containing one column of memory cells of each plane. The DRAM includes bit lines extending along the first axis in one of the sub-blocks, and is connected to one memory cell in each plane. The DRAM has global bit lines. One or more global bit lines are connected to the bit lines in each sub-block. The DRAM also has sense amplifiers each connected to one of the global bit lines.