Hybrid Resistive Memory Circuit with Multi-Level Stacking
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Solution Overview
Problem
Existing resistive memory technologies lack a combination of properties necessary for certain applications, such as data retention, drift, and robustness, which cannot be met by a single memory technology.
Innovation Solution
A memory circuit comprising a transistor layer with multiple levels of memory elements, including phase change memory elements, ferroelectric tunnel junction memory elements, and filament switching resistive memory elements, such as conductive bridging memory elements, positioned in separate levels with dedicated interconnection levels for each type, allowing for the integration of different memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory technology is used, then device complexity is reduced, but the combination of properties (data retention, drift, robustness) required for certain applications cannot be achieved
Solution Approach 1:
The patent merges multiple memory technologies (phase change memory, ferroelectric tunnel junction memory, oxide RAM, conductive bridging memory) into a single hybrid memory device structure. This allows the device to combine the advantageous properties of each memory type - such as high data retention from phase change memory and low programming current from conductive bridging memory - while maintaining a unified device architecture that manages complexity through integration rather than separation.
Solution Approach 2:
The hybrid memory device is designed to perform multiple functions simultaneously using different memory elements within the same device. The same device structure can leverage phase change memory for high retention applications, ferroelectric tunnel junction memory for non-volatility, oxide RAM for robustness, and conductive bridging memory for low power consumption, making the device universally applicable to various storage requirements without needing separate specialized devices.
2Reliability
If multiple memory elements are integrated in different levels, then the combination of properties is enhanced, but device complexity increases
Solution Approach 1:
The patent resolves the complexity of integrating multiple memory types by utilizing the vertical dimension - stacking memory elements in different levels (first level and second level) rather than attempting to place all elements in a single plane. This three-dimensional arrangement allows distinct memory technologies to coexist without lateral interference, with dedicated interconnection levels providing structured routing paths that manage the complexity of multi-level integration while enabling enhanced property combination.
3Ease of operation
If dedicated interconnection levels are provided for each memory type, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The patent segments the interconnection structure by providing dedicated interconnection levels for different memory element types. The first interconnection level is dedicated to routing first memory elements (such as phase change or ferroelectric tunnel junction memory), while the second interconnection level is dedicated to routing second memory elements (such as oxide RAM or conductive bridging memory). This segmentation isolates routing paths to simplify control and operation of each memory type while organizing the overall device architecture into manageable modular sections.
Data Source
AI summary
The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.