Memory Control Circuit Dynamic Delay Adjustment for DDR-SDRAM
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Solution Overview
Problem
Existing memory control circuits for DDR-SDRAMs face challenges in ensuring proper data acquisition due to irregularities in the wafer fabrication process, leading to instability in delay durations and high overhead in identifying and setting the optimum delay duration, which affects data retention and transfer efficiency.
Innovation Solution
A memory control circuit with a clock generation circuit, retention circuits, a data acquisition timing judgment unit, and a data strobe signal correction unit that maintains the significant state of the data strobe signal until the correct data acquisition timing is judged, ensuring reliable data transfer regardless of fabrication irregularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a pre-specified delay duration is used in accordance with design comparisons of data strobe signal phases and clock signal phases, then the memory control circuit can be fabricated as a portion of a semiconductor integrated circuit, but proper data acquisition will not always be guaranteed due to irregularities in wafer fabrication process
Solution Approach 1:
The patent implements dynamic delay adjustment by allowing the delay duration to vary based on detected phase relationships between data strobe signals and clock signals. The memory control circuit adjusts the delay in real-time to compensate for fabrication irregularities, transitioning from a static pre-specified delay to a dynamic adaptive delay that ensures reliable data acquisition across different manufacturing conditions
Solution Approach 2:
The patent changes the delay duration parameter dynamically based on the detected phase relationship between data strobe signals and clock signals. When the data strobe signal phase is advanced or delayed relative to the clock signal phase, the system adjusts the delay parameter accordingly to maintain proper data acquisition timing, thereby resolving the contradiction between ease of fabrication and data acquisition reliability
2Reliability
If the identification and setting of the optimum delay duration is performed at memory initialization and at certain time intervals as program operations, then the optimum delay duration can be identified and Read data can be latched within an effective range, but the overhead is very large which is impractical
Solution Approach 1:
The memory control circuit performs self-adjustment of the delay duration by automatically detecting the phase relationship between data strobe signals and clock signals. The system uses its own internal signals to determine the optimal delay without requiring external program operations or initialization routines, thereby eliminating the large overhead associated with repeated identification and setting operations while maintaining reliable data latching
Solution Approach 2:
The patent implements a feedback mechanism where the memory control circuit continuously monitors the phase relationship between data strobe signals and clock signals and adjusts the delay duration accordingly. This closed-loop feedback system eliminates the need for repeated program operations to identify and set the optimum delay duration, significantly reducing overhead time while ensuring data is always latched within the effective range
Data Source
AI summary
A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a significant state of a data strobe signal, which is provided together with the data signal. The memory control circuit controls data acquisition from the retention circuit in accordance with the clock signal. A data acquisition timing judgment unit, by monitoring the clock signal, judges whether or not a timing of the data acquisition has arrived. A data strobe signal correction unit maintains the significant state of the data strobe signal until it is judged that the data acquisition timing has arrived.