Variable Resistance Memory Storage Circuit Offset Correction
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Solution Overview
Problem
Existing storage circuits face challenges in precisely reading data from memory cells with variable-resistance elements due to variations in memory cell characteristics, load transistors, grounding transistors, and arrangement positions, leading to difficulties in setting common reference voltages and offset voltage cancellation.
Innovation Solution
A storage circuit with a memory cell array, selection circuit, conversion circuit, reference signal generation circuit, sense amplifier, correction data storage, and correction circuit that adjusts physical properties like voltage or current values for each sense amplifier to accurately determine data stored in memory cells, using correction data to customize the reference signal and correct offset voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common reference voltage is applied to all sense amplifiers, then the device complexity is reduced, but the measurement precision deteriorates due to variations in memory cell characteristics and bit line voltages across different columns
Solution Approach 1:
The patent divides the single common reference voltage into multiple column-specific reference voltages (first reference voltage for first column, second reference voltage for second column, etc.). Each sense amplifier receives a reference voltage tailored to its specific column, allowing independent optimization for that column's bit line voltage characteristics and memory cell variations.
Solution Approach 2:
Each sense amplifier is provided with a reference voltage that is locally optimized for its specific column. The reference voltage generation circuit generates different reference voltages for different columns based on their respective bit line voltage distributions, ensuring that each sense amplifier operates with the most suitable reference for its local conditions.
2Adaptability or versatility
If the reference voltage is set to accommodate the widest range of bit line voltage variations, then the adaptability is improved, but the measurement precision deteriorates because the reference voltage cannot be optimized for each specific column
Solution Approach 1:
Instead of using a single reference voltage that must accommodate all columns, the patent segments the reference voltage generation into column-specific circuits. Each column has its own reference voltage generated based on that column's bit line voltage characteristics, allowing precise optimization for each column while maintaining the ability to handle variations across different columns.
3Measurement precision
If offset voltage cancellation is implemented in each sense amplifier, then the measurement precision is improved, but the device complexity increases due to additional correction circuits and test procedures
Solution Approach 1:
The patent performs offset voltage cancellation during the manufacturing test phase rather than during normal operation. Test circuits are provided to measure and determine offset voltages for each sense amplifier, and correction values are calculated and stored in correction memory. This preliminary action allows offset cancellation to be implemented without adding complex correction circuits to the main device structure.
Solution Approach 2:
The device uses its own test circuits and correction memory to automatically determine and store offset voltage correction values for each sense amplifier. The correction data is stored in correction memory associated with each sense amplifier, allowing the device to self-correct offset voltages during normal operation without requiring external intervention or complex additional correction hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise determination of data stored in memory cells by customizing physical properties for each sense amplifier, effectively addressing variations and ensuring accurate data reading across the storage circuit.
Implementation Method 1
Each of the memory cells MCi is formed of a variable-resistance element such as a magnetoresistive element, and set at a high or low resistance
Implementation Method 2
a sense amplifier SA that determines data stored in the memory cell by amplifying a difference between a bit line voltage and a reference voltage
Data Source
AI summary
A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.