Memory Controller Priority-Based ECC for Approximate Memory
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Solution Overview
Problem
As deep neural networks increase in complexity, the power consumption of memory devices used in artificial intelligence applications rises due to the need for frequent data refresh, which can lead to increased bit error rates and reduced accuracy in calculations, especially when operating as approximate memory devices with slower refresh rates.
Innovation Solution
A memory controller that employs a priority-based ECC to convert insignificant bits into parity bits, reducing the number of bits stored in memory devices and allowing for a slower refresh rate while maintaining data accuracy by protecting significant bits with parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the refresh rate of memory device is reduced to lower power consumption, then power consumption is reduced, but bit error rate increases and calculation accuracy deteriorates
Solution Approach 1:
The patent segments data bits into significant bits and insignificant bits, applying different protection strategies to each segment. Significant bits are protected with parity bits while insignificant bits are stored without protection, enabling selective error correction that maintains accuracy for critical data while reducing overall refresh requirements and power consumption.
Solution Approach 2:
The patent applies different quality levels of error protection to different parts of the data. High-quality protection (parity bits) is applied locally to significant bits that require accuracy, while low-quality or no protection is applied to insignificant bits, optimizing the balance between power consumption and calculation accuracy based on local data importance.
2Measurement precision
If more bits are stored in memory device, then data accuracy is maintained, but power consumption increases due to frequent refresh
Solution Approach 1:
The patent extracts and identifies insignificant bits from the data that can be tolerate errors, separating them from significant bits that require protection. By taking out the insignificant portion, the system reduces the amount of protected data stored in memory, thereby reducing refresh operations and power consumption while maintaining sufficient data accuracy for neural network calculations.
Solution Approach 2:
The patent applies partial error protection only to significant bits rather than all data bits. This partial action approach provides sufficient error correction for critical data while avoiding the excessive power consumption that would result from protecting all bits equally, achieving an optimal balance between data accuracy and energy efficiency.
3Reliability
If all bits are protected with parity bits, then data accuracy is maintained, but memory capacity and refresh overhead increase
Solution Approach 1:
The patent segments data into significant and insignificant bits, applying parity protection only to significant bits. This segmentation reduces the total number of parity bits required compared to protecting all bits, thereby reducing memory capacity requirements and refresh overhead while maintaining data accuracy for the most important data portions.
Solution Approach 2:
The patent implements partial error protection by applying parity bits only to significant bits rather than all data bits. This partial protection strategy reduces memory capacity requirements and refresh overhead compared to full protection, while still maintaining sufficient data accuracy for neural network operations where not all bits contribute equally to calculation results.
Data Source
AI summary
A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.