Twisted Wordline Straps for MRAM Resistance Reduction
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Solution Overview
Problem
The implementation of poly-Si material for wordlines in magnetic random access memory (MRAM) devices causes a performance bottleneck due to resistance issues, and the use of metal contacts in higher layers increases the bitcell area and limits routing capabilities.
Innovation Solution
The introduction of twisted wordline structures that route metal layers from the gate of access transistors to magnetic tunnel junction (MTJ) memory elements, using dummy bitcells to strap wordlines to lower metal layers, reducing parasitic resistance and maintaining top layers for routing, while allowing for balanced parasitics across different metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal contact is implemented in higher layers to address resistance bottleneck, then wordline resistance is reduced, but bitcell area increases and routing layers are occupied
Solution Approach 1:
The patent implements wordline strapping in lower metal layers (M2, M3) rather than using higher layers for metal contacts. This dimensional shift allows the wordline resistance to be addressed without occupying upper routing layers, thereby maintaining bitcell area efficiency while reducing resistance through the use of dummy bitcells and twisted wordline structures in lower layers.
Solution Approach 2:
The patent introduces dummy bitcells as intermediary structures that contain the wordline strapping functionality. These dummy bitcells serve as mediators between the active bitcells and the metal layers, allowing the wordline resistance to be reduced through strapping without directly impacting the active memory array area or routing capabilities.
2Reliability
If metal contact is implemented in higher layers to reduce resistance, then wordline resistance is improved, but routing capabilities are limited
Solution Approach 1:
The patent resolves the routing flexibility issue by implementing wordline strapping in lower metal layers (M2, M3) rather than consuming upper layers. This dimensional separation ensures that the routing layers remain available for interconnect purposes, maintaining routing flexibility while still addressing wordline resistance through the dummy bitcell structures in lower layers.
3Ease of manufacture
If poly-Si material is used for wordlines, then manufacturing is simplified, but resistance performance deteriorates
Solution Approach 1:
The patent employs a composite structure where poly-Si wordlines are combined with metal strapping layers (M2, M3). The poly-Si material maintains ease of manufacture through standard CMOS processes, while the metal strapping layers are added to reduce resistance. This composite approach allows both manufacturing simplicity and performance improvement to coexist.
Solution Approach 2:
The metal strapping layers act as intermediaries between the poly-Si wordlines and the ground/reference potentials. These metal layers mediate the resistance issue by providing low-resistance paths that complement the poly-Si wordlines, allowing the poly-Si material to remain used for ease of manufacture while the metal layers compensate for the resistance deficiency.
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.