Memory Rank Data Strobe Delay Training Bypassing Buffer
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Solution Overview
Problem
In memory systems, ensuring reliable data transfer between volatile and non-volatile memory ranks is challenging due to differences in transmission rates across channels, affecting the reliability of data signal transfer.
Innovation Solution
A method for determining and adjusting the delay of the data strobe signal between memory ranks without involving the data buffer, using training data and commands from a memory controller to synchronize data transfer between volatile and non-volatile memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transfer between memory ranks passes through the data buffer, then data transfer is simplified, but transfer speed and reliability are reduced
Solution Approach 1:
The patent extracts the data buffer from the training data transfer path between memory ranks. Training data and data strobe signals are transmitted directly from the first memory rank to the second memory rank without passing through the data buffer, while normal data operations still use the data buffer. This selective removal of the buffer for training operations improves transfer speed and reduces latency without completely eliminating the buffer's protective function.
Solution Approach 2:
The patent uses the data strobe signal as an intermediary to enable direct communication between memory ranks during training. The data strobe signal carries timing information that allows the second memory rank to synchronize and capture training data directly from the first memory rank, establishing a direct transfer path that bypasses the data buffer while maintaining signal integrity through the strobe-mediated synchronization.
2Reliability
If delay training is performed without data buffer involvement, then transfer reliability is improved, but system complexity increases
Solution Approach 1:
The patent performs delay training as a preliminary action before normal data operations. The training process determines the optimal delay value for the data strobe signal in advance, accounting for variations in transmission rates between different memory ranks and channels. This preliminary calibration ensures that subsequent data transfers occur with optimized timing parameters, improving reliability without requiring complex real-time adjustments during operational data transfer.
Solution Approach 2:
The patent adjusts the delay parameter of the data strobe signal based on training results. By varying the delay value and observing transfer quality during training, the system identifies the optimal delay setting that compensates for channel-specific transmission rate differences. This parameter optimization enables reliable direct transfer between memory ranks, with the determined delay value being stored and applied during normal operations to maintain reliability.
3Manufacturing precision
If data strobe signal delay is not adjusted, then system operation is simpler, but data transfer accuracy deteriorates
Solution Approach 1:
The patent implements self-service through automatic delay training and adjustment. The memory system performs self-calibration by having the second memory rank sense training data with varying data strobe signal delays, automatically determining the optimal delay value without external intervention. This self-adjusting mechanism ensures accurate data transfer while minimizing the need for manual configuration or complex external synchronization control, as the system autonomously optimizes its own timing parameters.
Data Source
AI summary
Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.