DRAM Self-Refresh Exit Delay Reduction via DLL Intermittent Activation
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Solution Overview
Problem
Semiconductor devices with self-refresh mode experience long delays in issuing commands after exiting self-refresh mode due to asynchronous refresh operations and DLL circuit locking issues, which hinder efficient data access and increase power consumption.
Innovation Solution
Implementing a control method that allows for periodic refresh operations on a smaller number of memory cells during self-refresh mode, enabling faster exit from self-refresh mode by activating the DLL circuit intermittently, and issuing commands sooner after exit, while maintaining compliance with DRAM standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor device enters self-refresh mode to reduce power consumption, then power consumption is reduced, but the time required to issue commands after exiting self-refresh mode increases
Solution Approach 1:
The patent applies preliminary action by performing a partial refresh operation on a subset of memory banks (e.g., even-numbered banks) during the self-refresh exit period, before all refresh operations are complete. This allows the device to prepare for command issuance in advance, reducing the waiting time after exit while still maintaining data integrity across all banks.
Solution Approach 2:
The patent segments the refresh operation into multiple independent parts: a first refresh operation on a first subset of memory banks and a second refresh operation on a second subset of memory banks. These operations can proceed independently and in parallel, allowing the device to exit self-refresh mode sooner while refresh operations continue on remaining banks.
2Loss of energy
If refresh operations are performed asynchronously with external clock signal during self-refresh mode, then power consumption is reduced, but the refresh operation may conflict with self-refresh exit command timing
Solution Approach 1:
The patent implements dynamic control of refresh operations by allowing the refresh timing and scope to adapt based on the self-refresh exit command timing. The system dynamically adjusts which memory banks are refreshed at which times, enabling flexible coordination between asynchronous refresh operations and synchronous command issuance requirements.
Solution Approach 2:
The patent changes the parameters of refresh operations during self-refresh mode, specifically varying the number and selection of memory banks refreshed at different times. This parameter variation allows the system to optimize between power consumption, refresh completeness, and command issuance timing flexibility.
3Loss of energy
If the DLL circuit operation is stopped during self-refresh mode, then power consumption is reduced, but the time required for DLL circuit to lock again after exiting self-refresh mode increases
Solution Approach 1:
The patent applies periodic action by implementing intermittent activation of the DLL circuit during self-refresh mode. Instead of keeping the DLL circuit completely stopped or continuously active, the system periodically activates it for brief intervals to maintain locking capability while minimizing power consumption, thus reducing the re-lock time after exit.
Data Source
AI summary
A method for operating a dynamic random access memory device includes providing a clock signal to a clock terminal of the dynamic random access memory device, selecting one of a first operating mode and a second operating mode of the dynamic random access memory device, the first operating mode, when selected, corresponding to the DRAM periodically refreshing a first number of word lines, and the second operating mode, when selected, corresponding to the DRAM periodically refreshing a second number of word lines different from the first number, and providing a self-refresh command to a command terminal of the dynamic random access memory device.