2T0C Memory Cell With Double-Gate Transistor for Leakage Reduction
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Solution Overview
Problem
Existing storage cells for dynamic random access memory (DRAM) require frequent data refresh due to leakage, leading to high power consumption and performance issues during read/write operations, and face challenges with crosstalk in 2T0C structures.
Innovation Solution
A storage cell design with a read transistor having a double-gate structure and a write transistor that omits the need for a capacitor, utilizing a back-gate effect to adjust voltage and reduce leakage, and a shared bit-line configuration to minimize the number of bit-lines and word-lines, thereby reducing refresh frequency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional 1T1C storage cell structure is used, then the storage function is achieved, but frequent data refresh is required due to leakage, leading to high power consumption
Solution Approach 1:
The patent extracts and removes the capacitor component from the traditional 1T1C storage cell structure, transitioning to a 2T0C configuration. This extraction eliminates the leakage path through the capacitor, significantly reducing power consumption while maintaining data retention through the transistor gate voltage storage mechanism
Solution Approach 2:
The patent changes the fundamental operating parameters of the storage cell by using two transistors with different threshold voltages and eliminating the capacitor. The storage mechanism shifts from charge-based (capacitor) to voltage-based (transistor gate), fundamentally altering how data is stored and reducing refresh requirements
2Productivity
If a conventional storage cell structure is used, then basic storage operation is achieved, but read/write performance is degraded due to leakage and high refresh frequency
Solution Approach 1:
By removing the capacitor and its associated leakage paths, the patent enables faster read/write operations without the performance penalties of frequent refreshing. The 2T0C structure allows for more efficient signal transmission and data access
Solution Approach 2:
The patent introduces dynamic threshold voltage adjustment through the back-gate effect, allowing the transistors to adapt their operating characteristics in real-time. This dynamic control optimizes read/write performance by adjusting device parameters based on operational requirements
3Loss of energy
If a 2T0C storage cell structure is used, then power consumption is reduced, but crosstalk problems occur during read operations
Solution Approach 1:
The patent applies local quality control by using transistors with different threshold voltages (VT1 and VT2) in specific configurations. The read transistor has a higher threshold voltage than the write transistor, creating localized voltage domains that prevent crosstalk during read operations while maintaining low power consumption
Solution Approach 2:
The patent introduces a back-gate mechanism as an intermediary control element that mediates between the read and write transistors. This back-gate allows for independent control of the read transistor's threshold voltage, preventing crosstalk with adjacent cells during read operations
4Ease of operation
If separate read and write bit-lines are used, then data access is simplified, but the number of bit-lines and word-lines increases, complicating the array structure
Solution Approach 1:
The patent merges the read and write bit-lines into a shared bit-line structure, reducing the total number of bit-lines and word-lines in the memory array. This sharing is enabled by the 2T0C cell structure where the same bit-line can serve both read and write operations through controlled transistor activation
Solution Approach 2:
The shared bit-line is designed to perform multiple functions - serving as both a read bit-line and a write bit-line depending on the operational mode. This multi-functionality reduces the overall complexity of the memory array while maintaining ease of data access through proper transistor control sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in lower leakage currents, reduced refresh frequency, and improved performance of read/write operations, while also addressing crosstalk issues in storage arrays by ensuring only the necessary storage cells are accessed during data reading and writing.
Implementation Method 1
the gate of the read transistor has a back-gate effect, setting two gates facilitates the first gate to adjust the applied voltage according to the magnitude of the voltage of the second gate (which can be regarded as an assistant gate), to ensure the conduction between the source and drain of the first transistor
Data Source
AI summary
A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.