Digital Storage TRIZ Cases

An addressed search circuit emulates match conditions within a CAM array to enable individual row testing.

A common gate input buffer circuit amplifies signals using cross-coupled PMOS structures and continuous time linear equalizer stages.

Shared detecting units reduce write driver area and improve layout efficiency for high-capacity memory.

A memory controller calibrates an under-test signal phase by issuing low-power status commands and comparing responded data against predetermined values.

A memory controller determines optimal phase combinations to widen voltage determination ranges for data signals.

A single-port SRAM design uses a write buffer to generate negative voltage for improved read and write margins.

A self-nulling preamplifier applies additional charge to non-floating bit lines during the read cycle.

A memory physical layer interface circuit uses clock generation modules and FIFO buffers to synchronize data transmission between a controller and device.

A semiconductor memory device divides external clock signals into odd and even period internal clocks to drive separate input units.

Segmenting memory into three circuits with oxide semiconductor transistors reduces overhead power and break-even time for cache leakage management.

Auxiliary driver circuit suppresses lower write potential fluctuations during sensing operations, accelerating read speed.

Periodic sampling reduces standby current while maintaining stable reference voltages near VSS for embedded dynamic random access memory.

A memory circuit architecture divides the array into halves using partial wordline drivers and dual bitline sets to support flexible cell configurations.

Adjustable preamble cycles condition the communication path before data transmission, reducing intersymbol interference and skew in digital links.

Discharging bit lines to ground eliminates continuous voltage swings, cutting AC power consumption during idle periods.

A semiconductor device incorporates a delay selection signal generation circuit to produce internal read and write signals for data scrub operations.

A compute-in-memory device uses a pre-computation circuit to generate adder outputs from input parameters.

Storing boot code in an internal register eliminates repeated external retrieval, reducing initialization time while maintaining correctness.

Standard memory cells execute sum-of-products functions via modified sense amplifiers, reducing cell size while retaining RAM compatibility.

Segmented reference cells generate a summed current that compensates for mismatching and body effects during read operations.

An oxygen gettering layer blocks manganese diffusion and oxygen oxidation to maintain exchange bias in spintronic devices.

Circuit reduces current consumption by detecting actual voltage differences and dynamically adjusting amplification factors to prevent signal distortion.

A semiconductor internal voltage generator uses a selector to switch target voltages during operational phases.

Virtual supply voltage adaptation circuit links inverter and level converter nodes, reducing standby leakage during zero-state reads.

A shared sense amplifier control circuit activates amplifiers after column selection, reducing device area while improving write speeds.

A 2T0C memory cell uses a double-gate read transistor to reduce leakage current without requiring a storage capacitor.

Replacing compensation nets with a current limiter reduces area and ringing while increasing slew rates.

A write-assist column adjusts the voltage array to lower the required write voltage for SRAM cells.

A phase-change memory device switches between differential and single-ended reading modes using control switches.

Shorting reference lines in matched MTJ arrays stabilizes sense references, matching RC time constants to reduce area and power overheads.

A common refresh delay unit controls bank-active signals across multiple semiconductor memory banks.

A bus inversion decoding block aligns address signals for parallel processing within a semiconductor memory device.

A sense amplifier driving device uses a bias current generation unit and latch unit to amplify bit line voltage signals.

A programmable resistance element stores configuration data in a latch circuit to enable dynamic reconfiguration of integrated circuit functions.

Decoupling bit line pairs prevents capacitance doubling and bit cell instability during address matches.

A semiconductor sampling timing generator randomizes refresh intervals to reduce bit errors in dynamic random access memory devices.

A conductive cap wraps around a memory pillar to enable upper metal line integration.

Peripheral input output driving blocks reduce Y hole area and global line loading by relocating drivers from the memory array.

Segmenting the multiplier into a weight-shifted array eliminates analog sensing and routing congestion while improving precision.

Segmented phase-change layers reduce resistance drift and cross-talk to achieve three stable states.

Segmenting the decoder allows independent voltage application to selection transistors, resolving insufficient operation margin in high-density memory arrays.

A semiconductor device generates strobe signals from phase-shifted internal clocks during masking clock enable periods.

A memory system skips internal read operations during consecutive masked write commands to the same address.

A magnetoresistive effect element uses antiferromagnetic coupling in its free layer to stabilize magnetic states for reliable memory operation.

Write logic dynamically assigns permissible driver counts to parallel bit lines, optimizing charge pump efficiency and throughput.

Segmented bi-directional resistive elements resolve the speed-area trade-off, achieving SRAM-like performance while maintaining compact cell area.

A memory system uses a current source and selector transistor to program resistive random-access memory cells.

Layered segmented main word lines distribute jump contacts to reduce parasitic resistance and increase sensing margin.

A write shifter shifts commands through stages to control input buffer enablement and disablement timing.