Three-Circuit Memory Device with Oxide Semiconductor Transistor
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Solution Overview
Problem
In semiconductor devices, particularly CPUs, the downsizing of transistors leads to increased power consumption due to leakage current, with cache elements contributing significantly to leakage power, and existing nonvolatile memory solutions like flash memories are inadequate for high-speed operation and frequent data rewrites.
Innovation Solution
A memory device with a three-circuit structure, including a first circuit for data retention during power supply, a second circuit for saving and retaining data during power off, and a third circuit using an oxide semiconductor transistor and capacitor for extended data retention, allowing for fine-grained power gating and reduced overhead power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is implemented to reduce leakage power in cache, then power consumption is reduced, but overhead power for data saving and recovery increases the break even time
Solution Approach 1:
The memory system is segmented into three distinct circuits: a first circuit for data retention during power supply, a second circuit for saving data during power off, and a third circuit using oxide semiconductor transistors for extended data retention. This segmentation allows data to be progressively transferred through circuits with increasing retention capabilities, enabling power gating with reduced overhead time and power.
Solution Approach 2:
Data is saved in advance to the second circuit before power is completely cut off, and the third circuit is prepared with oxide semiconductor transistors that can retain data for extended periods without power. This preliminary action reduces the overhead time required for data saving and recovery, thereby reducing the break even time for power gating operations.
2Duration of action of stationary object
If flash memory is used for nonvolatile storage, then data retention during power off is achieved, but operation speed and data rewrite capability are insufficient
Solution Approach 1:
Different circuits are assigned different retention qualities based on their function: the first circuit provides short-term retention during power supply, the second circuit provides medium-term retention during power off, and the third circuit with oxide semiconductor transistors provides long-term retention. This local differentiation of retention qualities allows the system to achieve both fast operation and extended data retention without relying on slow flash memory.
Data Source
AI summary
Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.