Synchronous Input Buffer Control Using Write Shifter
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Solution Overview
Problem
Truncated input buffer disable periods in memory devices can lead to partial reset conditions of the DQS clock generator, resulting in memory failures where data input bits are dropped.
Innovation Solution
Implementing synchronous input buffer control circuitry to ensure deterministic enablement and disablement of data and DQS input buffers, with a minimum pulse width for disable periods and adaptive increase based on write-to-write spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input buffer is disabled to save power during large separation between write commands, then power consumption is reduced, but the DQS clock generator may not properly reset resulting in partial reset conditions
Solution Approach 1:
The patent applies preliminary action by extending the input buffer disable period before the next write command to ensure the DQS clock generator has sufficient time to complete its reset. This proactive extension prevents partial reset conditions from occurring, ensuring the clock generator is fully reset before the next write operation begins, thus resolving the contradiction between power savings and reset completeness.
2Productivity
If the input buffer disable period is shortened to increase write command frequency, then productivity is improved, but memory failures occur due to truncated reset periods
Solution Approach 1:
The patent applies dynamics by making the input buffer disable period adaptive rather than fixed. The disable period is dynamically adjusted based on the write-to-write timing interval - when write commands are frequently issued, the disable period is extended to ensure proper reset, while allowing shorter periods when timing permits. This dynamic adjustment enables the system to maintain data integrity while optimizing write command frequency.
3Use of energy by moving object
If the input buffer is disabled during large separation between write commands, then power is saved, but asynchronous behavior of input buffer enable circuitry causes data bits to be dropped
Solution Approach 1:
The patent applies feedback by monitoring the actual write-to-write timing intervals and using this information to control the input buffer disable period. The system receives feedback about when write commands are issued and adjusts the disable period accordingly, ensuring that the buffer remains enabled long enough to prevent data bit loss while still allowing power savings when appropriate timing conditions are met.
Data Source
AI summary
A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.