Self-Nulling Preamplifier for Memory Bit Line Offset
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Solution Overview
Problem
Conventional integrated circuit memory designs face limitations in read signal margin due to manufacturing variations causing sense amplifier offset and the capacitor divider effect, which restrict the minimum size of memory cells and increase costs per bit.
Innovation Solution
The introduction of a self-nulling preamplifier that eliminates offset by applying additional charge to non-floating bit lines during the read cycle, allowing for reliable detection of small signal differentials and improving read signal margin, along with a reference memory cell configuration that provides a reliable reference for sense amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional latching sense amplifier circuits are used to read data states, then the sense amplifier can detect bit line signals, but manufacturing process variations cause variable offsets that limit the ability to reliably detect very small signal differences
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a specific voltage level before the read operation begins. This precharging step establishes a known initial state that compensates for manufacturing variations and offsets in the sense amplifier, enabling reliable detection of small signal differences despite process variations.
Solution Approach 2:
The patent changes the voltage parameter of the bit lines dynamically during the read cycle. By transitioning bit lines from a precharged state to a floating state, and adjusting voltage levels at different phases, the system optimizes signal detection while compensating for sense amplifier offsets caused by manufacturing variations.
2Ease of operation
If floating bit lines are used for the sensing portion of the read cycle in memories that store data on charge storage capacitors, then the read operation can be performed, but a capacitor divider effect reduces the read signal margin
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a specific voltage level before the read operation begins. This precharging step establishes a known initial state that compensates for manufacturing variations and offsets in the sense amplifier, enabling reliable detection of small signal differences despite process variations.
Solution Approach 2:
The patent changes the voltage parameter of the bit lines dynamically during the read cycle. By transitioning bit lines from a precharged state to a floating state, and adjusting voltage levels at different phases, the system optimizes signal detection while compensating for sense amplifier offsets caused by manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the use of smaller memory storage devices, increasing memory capacity and reducing costs per bit while enhancing reliability, allowing memory cells to scale to smaller technology nodes.
Implementation Method 1
a self-nulling preamplifier that eliminates offset by applying additional charge to non-floating bit lines during the read cycle
Implementation Method 2
memories that store data on charge storage capacitors
Data Source
AI summary
An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle. Memory cells according to this invention can be configured to provide a reference cell for the reference bit line.