Memory System Masked Write Read Skipping
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Solution Overview
Problem
Current memory devices employing on-chip error correction codes (ECC) face inefficiencies in performing masked write operations, leading to increased current consumption due to the need for internal read-modification-write operations.
Innovation Solution
A memory system that includes a controller and memory device capable of skipping internal read operations when consecutive masked write commands are inputted for the same address, using a read blocking signal to enable error correction and parity bit generation, thereby reducing current consumption during masked write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal read operation is performed during masked write operation, then error correction can be performed, but current consumption increases
Solution Approach 1:
The patent applies preliminary action by determining whether consecutive masked write commands target the same address before executing the read operation. The control logic checks the address comparison result in advance, and only performs the read operation when necessary (i.e., when addresses differ). This prevents unnecessary read operations that would consume current, while ensuring error correction is performed when actually needed for data integrity.
2Use of energy by moving object
If internal read operation is skipped for consecutive masked write commands to same address, then current consumption is reduced, but error correction may be compromised
Solution Approach 1:
The patent implements feedback through the address comparison mechanism that continuously monitors whether consecutive masked write commands target the same address. The control logic uses this feedback to dynamically decide whether to perform the read operation: if addresses are the same, the read is skipped (saving current); if addresses differ, the read is performed (ensuring error correction). This feedback-based decision-making resolves the contradiction by adapting the error correction process to actual operational needs.
Data Source
AI summary
A memory system may include: a controller suitable for transmitting a command, an address and write data, and receiving read data, the command including a write command, a read command and a masked write command; and a memory device suitable for sequentially performing an internal read operation, an internal modification operation and an internal write operation in response to the masked write command while skipping the internal read operation when the masked write commands for the same address are consecutively inputted after the write command is inputted.