Compute-in-Memory Device Pre-computation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Artificial intelligence (AI) networks, such as deep neural networks, require matrix multiplication operations that involve significant data movement from memory to computing circuits, leading to time and energy consumption, which hinders performance in compute-in-memory (CIM) systems.
Innovation Solution
The CIM technology employs memory cells as nodes in neural networks, where data is written into memory cells, and their equivalent resistances or transduction values are altered to act as weights, enabling in-memory multiplication and addition operations, reducing data movement and circuit area, and improving execution efficiency by using a digital CIM device with a pre-computation circuit, adder tree, and accumulator to perform multiply-accumulate operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is moved from memory to computing circuits for matrix multiplication, then computation can be performed, but time and energy consumption increase
Solution Approach 1:
The patent merges the memory function and computing function into a single integrated structure. Memory cells perform both data storage and multiply-accumulate operations, eliminating the need to move data between separate memory and computing circuits. This integration directly resolves the contradiction by enabling computation at the memory location, thereby improving computation speed while reducing energy consumption associated with data movement.
2Productivity
If data is moved from memory to computing circuits, then computation can be performed, but time consumption increases
Solution Approach 1:
The patent combines memory and computing functions into an integrated architecture where memory cells perform computation in-place. This eliminates the data movement step between separate memory and computing circuits, directly reducing data movement time and improving overall computation speed.
Solution Approach 2:
The patent implements pre-computation of weight values and stores them directly in the memory cells before the actual computation is needed. This preliminary preparation of data in the memory allows immediate computation without additional data movement time when computation is triggered, thereby reducing time consumption.
3Loss of energy
If memory cells are used for computation, then data movement is reduced, but circuit complexity increases
Solution Approach 1:
The patent makes memory cells multi-functional by enabling them to perform both data storage and compute operations. This universal design allows the same hardware structure to serve dual purposes, reducing the need for additional dedicated computing circuits and thereby limiting the increase in overall circuit complexity while achieving energy reduction through eliminated data movement.
Solution Approach 2:
The patent uses the existing memory cell structure and replicates it to form the computing array, rather than introducing entirely new computing circuit designs. This approach leverages the proven memory cell architecture for computation, minimizing the increase in circuit complexity while achieving the energy benefits of in-memory computing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption and enhances execution efficiency by enabling fast-path and normal-path operations within the CIM device, optimizing energy usage and computation speed for AI applications.
Implementation Method 1
each of the memory cells is configured to multiply a respective bit of input data by a respective bit of a weight to obtain a respective bit of an adder input
Data Source
AI summary
Compute-in memory (CIM) devices are provided. A memory is configured to multiply input data by a weight to obtain an adder input. An addition circuit is configured to receive the adder input to provide an adder output, and includes a pre-computation circuit and an adder tree. The pre-computation circuit includes a parameter extractor and a parameter identification circuit. The parameter extractor is configured to extract an input parameter from the adder input. The parameter identification circuit is configured to provide a pre-computation result corresponding to the input parameter as the adder output when determining that the input parameter is present in a parameter table, and provide a control signal when determining that the input parameter is not present in the parameter table. The adder tree is configured to provide the adder output according to the adder input in response to the control signal.