SMT MRAM Reference Circuit Read Disturb Compensation
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Solution Overview
Problem
Existing SMT MRAM read reference circuits are prone to disturbance during read operations and suffer from current mismatching due to second-order non-matching effects, which affects accurate determination of data states in SMT MRAM cells.
Innovation Solution
A read reference circuit is implemented in SMT MRAM arrays with pairs of reference SMT MRAM cells programmed for maximum and minimum resistance, generating a summed reference current that is not disturbed during read operations, and a compensation current is used to offset current variations caused by body effects in the gating transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read reference circuit is implemented in existing SMT MRAM, then data state determination is enabled, but the reference cell becomes prone to disturbance during read operations
Solution Approach 1:
The reference cell is divided into two separate cells (first reference cell and second reference cell) with different resistance states. These segmented reference cells are used in a differential configuration where one cell provides the reference current and the other provides a complement reference current, allowing accurate measurement without disturbing a single reference cell's state.
2Device complexity
If a simple reference current generation circuit is used, then device complexity is reduced, but current mismatching occurs due to second-order non-matching effects
Solution Approach 1:
The invention changes the resistance state parameters of the reference cells by programming one reference cell to have maximum resistance and the other to have minimum resistance. This parameter differentiation enables differential measurement that inherently compensates for second-order non-matching effects, achieving high current matching accuracy without requiring complex additional circuitry.
3Measurement precision
If reference cells are programmed for maximum and minimum resistance, then current mismatching is compensated, but the body effect in gating transistors causes current variations
Solution Approach 1:
The differential configuration of the reference cells creates a self-balancing system. When body effects cause current variations in one transistor, the differential comparison with the other reference cell provides a reference level that enables the sense amplifier to compensate for these variations, effectively using feedback through differential measurement to maintain current stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures accurate and undisturbed read operations by providing a stable reference current, effectively compensating for current mismatching and body effects, thereby enhancing the reliability of data state determination in SMT MRAM cells.
Implementation Method 1
a current of spin-polarized electrons can change the magnetic orientation of a free ferromagnetic layer of an MTJ via an exchange of spin angular momentum
Implementation Method 2
the spin direction rotates according to the directions of magnetic moment. The rotation of spin direction of the electrons in the ferromagnetic layers is the origin of a spin-torque to the magnetic moment
Implementation Method 3
This changes the MTJ element from a low resistance state to a high resistance state thus changing the logic state of the MTJ element
Data Source
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AI summary
An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.