Multiport SRAM Address Match Decoupling
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Solution Overview
Problem
Multi-port memory devices face challenges in coordinating access to storage elements, leading to unpredictable access times due to the need for wait states and arbitration, which affects performance.
Innovation Solution
The solution involves decoupling the bit line pair of one port from the storage nodes of the selected memory cell while coupling the bit line pair of the other port to ensure effective access, avoiding capacitance issues and bit cell instability by disabling the word line of one port when both ports access a common bit cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-port memory provides access to storage elements for multiple resources, then versatility and parallel access capability are improved, but access time becomes unpredictable due to wait states and arbitration
Solution Approach 1:
The patent applies preliminary action by detecting address matches between multiple ports before access occurs. The match detector compares addresses in advance, and the control circuit preemptively disables one port's word line when a match is detected, preventing simultaneous access conflicts before they can cause unpredictable wait states and arbitration delays.
Solution Approach 2:
The patent implements feedback through the match detector that continuously monitors address signals from multiple ports. When address matches are detected, this feedback information is fed to the control circuit, which then adjusts word line enablement to prevent conflicts, creating a closed-loop system that adapts access control based on real-time address comparisons.
2Adaptability or versatility
If both bit line pairs are coupled to storage nodes of a selected bit cell, then both ports can access the cell, but capacitance of the bit line pairs adversely impacts access and causes bit cell instability
Solution Approach 1:
The patent applies the extraction principle by removing one bit line pair's coupling to the storage nodes when an address match is detected. The control circuit disables the word line for one port, effectively extracting or disconnecting that port's bit line pair from the storage nodes, leaving only one bit line pair coupled to maintain stable access while still allowing both ports to access the cell through the shared data line.
Solution Approach 2:
The patent uses the data line as an intermediary element that both ports can access through without direct coupling of both bit line pairs to storage nodes. When address matches occur, the control circuit enables one port's bit line pair to access storage nodes while the other port accesses through the data line intermediary, resolving the capacitance conflict while maintaining access for both ports.
Data Source
AI summary
In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.