Memory Architecture with Partial Wordline Drivers
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Solution Overview
Problem
The migration of memory cell aspect ratio in silicon foundry processes poses a significant challenge due to the need for substantial redesign of periphery circuitry, which is time-consuming and expensive, as existing technologies are tailored to specific cell sizes or aspect ratios, making it difficult to transition between low and high aspect ratio cells.
Innovation Solution
A memory circuit architecture that divides the array into upper and lower halves, using partial wordline drivers and dual sets of bitlines where one set contacts and the other set feeds through memory cells, allowing for the reuse of a significant portion of the periphery circuitry, thereby accommodating changes in memory cell aspect ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cell aspect ratio is changed to accommodate different process geometries, then manufacturing ease and array density are improved, but periphery circuitry redesign is required which increases cost and time
Solution Approach 1:
The memory array is divided into multiple segments (e.g., upper and lower halves) that can be independently configured. This segmentation allows the periphery circuitry to remain unchanged while the memory cell aspect ratio is changed, as each segment can accommodate different cell geometries independently.
Solution Approach 2:
The periphery circuitry is designed to be universal and function with multiple memory cell aspect ratios. By creating a periphery architecture that can interface with both low aspect ratio cells (tall and skinny) and high aspect ratio cells (wide and short), the same peripheral components can serve multiple configurations without redesign.
2Area of stationary object
If memory cell aspect ratio is changed, then array density and footprint are improved, but periphery circuitry customization is required which increases expense
Solution Approach 1:
The memory array configuration is made dynamic to accommodate different cell aspect ratios. The array can be reconfigured or reinterpreted to work with both low and high aspect ratio cells while maintaining the same periphery circuitry, reducing the need for custom designs.
Solution Approach 2:
The invention changes the parameters of the memory array configuration rather than the periphery circuitry. By adjusting how the array is organized and accessed (e.g., row/column assignments, decoding schemes), the system can accommodate different cell geometries without modifying the expensive periphery components.
3Productivity
If process geometry is reduced for faster frequencies, then integration level and speed are improved, but memory cell aspect ratio changes require significant periphery redesign
Solution Approach 1:
The periphery circuitry is designed in advance to accommodate multiple memory cell aspect ratios. By preparing a universal peripheral architecture that can interface with different cell geometries before the actual memory array is finalized, the need for redesign when transitioning to smaller process geometries is eliminated.
Data Source
AI summary
Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines.