Pre-discharged Bit Lines for Low Power SRAM Sensing
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Solution Overview
Problem
Existing SRAM cell designs experience significant current leakage and high power consumption due to constant power requirements, leading to increased DC and AC power usage, especially as SRAM cell density and number increase.
Innovation Solution
The implementation of pre-discharged bit lines in a multi-port SRAM, where bit lines are held at zero volts when not accessed and energized to an intermediate voltage only during access, reducing DC leakage and AC power consumption by eliminating unnecessary voltage swings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are continuously pre-charged to logical high level to maintain SRAM cell operation, then the SRAM cell can maintain data and allow reading/writing, but DC power consumption increases due to current leakage
Solution Approach 1:
The patent applies periodic action by pre-charging bit lines only during active read operations rather than continuously. The bit lines are discharged to ground when not in use and pre-charged to Vdd only when a read operation is initiated, converting continuous power consumption into periodic power consumption that occurs only when data access is needed.
Solution Approach 2:
The patent implements dynamics by making the bit line voltage state changeable between two states: discharged (0V) during idle periods and pre-charged (Vdd) during active operations. This dynamic voltage control allows the system to adapt power consumption to actual operational needs, eliminating the static continuous pre-charge requirement of traditional designs.
2Ease of operation
If bit lines are pre-charged to logical high level before read operations, then read operations can be performed, but AC power consumption increases due to large voltage swings
Solution Approach 1:
The patent uses periodic action to pre-charge bit lines only during active read operations rather than maintaining continuous voltage swings. By discharging bit lines during idle periods and only pre-charging them when a read operation is initiated, the system eliminates unnecessary AC power consumption associated with continuous voltage transitions.
Solution Approach 2:
The patent converts the potentially harmful effect of discharged bit lines (which could slow down read operations) into a benefit by using the discharge state to eliminate AC power consumption during idle periods. The brief delay in pre-charging is acceptable because it eliminates continuous voltage swings, and the read operation can still complete successfully once pre-charging begins.
3Quantity of substance
If SRAM cell density and number of cells increase, then memory capacity increases, but power consumption increases due to cumulative current leakage
Solution Approach 1:
The patent applies periodic action at the system level by controlling groups of bit lines associated with specific memory blocks. When a particular memory block is accessed, only the associated bit lines are pre-charged, while bit lines for other blocks remain discharged. This selective periodic pre-charging allows memory capacity to scale without proportionally increasing power consumption.
Data Source
AI summary
A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential.