Bitcell Shifting Technique for Low Power Multipliers
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Solution Overview
Problem
Conventional binary multipliers consume substantial dynamic power and area due to the use of multiple logic gates, leading to routing congestion and excessive toggling activity.
Innovation Solution
A weight-shifted array with time-multiplex sensing is implemented, reducing bitline levels from n^2 to n and improving sensing precision, which enables a low power compute-in-memory (CIM) device that operates as a novel multiplier, eliminating analog sensing and reducing dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional binary multipliers are implemented with multiple logic gates, then multiplication function is achieved, but dynamic power consumption increases substantially
Solution Approach 1:
The conventional binary multiplier is segmented into a weight-shifted array structure where bitcells are organized in rows and columns with specific weight assignments. This segmentation allows the multiplication function to be distributed across memory elements rather than concentrated in logic gates, reducing dynamic power consumption while maintaining the multiplication capability.
Solution Approach 2:
The patent replaces the mechanical logic gate system with a memory-based system using bitcells arranged in a weight-shifted array. This substitution eliminates the need for complex logic gate networks and their associated dynamic power consumption, achieving multiplication through memory structure and sensing operations instead of traditional digital logic.
2Area of stationary object
If conventional binary multipliers use multiple logic gates, then multiplication operation is performed, but area footprint on chip increases
Solution Approach 1:
The multiplier function is segmented into a compact weight-shifted array of bitcells arranged in rows and columns. This segmentation allows efficient spatial utilization where each bitcell contributes to the multiplication result based on its position and weight, significantly reducing the chip area required compared to traditional logic gate implementations.
Solution Approach 2:
The bitcell array structure serves multiple functions: it stores data, performs multiplication through its weight-shifted configuration, and enables sensing operations. This multi-functionality eliminates the need for separate logic gate circuits, reducing the overall chip area while maintaining full multiplication capability.
3Device complexity
If multiple different gates are used for partial product and sum, then multiplication function is achieved, but routing congestion increases
Solution Approach 1:
The patent employs a homogeneous array of identical or similar bitcells arranged in a weight-shifted configuration, replacing the heterogeneous mix of different logic gates (NAND2, XOR, half-adder, full-adder). This homogeneity simplifies the routing structure, as uniform cell interfaces and signaling schemes are used throughout, thereby reducing routing congestion and improving manufacturability.
4Measurement precision
If conventional binary multipliers are implemented with multiple logic gates, then multiplication is performed, but sensing precision is insufficient
Solution Approach 1:
The patent replaces the logic gate-based computation system with a memory-based sensing system. The weight-shifted bitcell array enables precise sensing of multiplication results through dedicated sensing circuits that read the memory states directly, achieving high sensing precision while eliminating the dynamic power consumption associated with logic gate toggling.
Data Source
AI summary
Various implementations described herein are directed to circuitry having a bitcell array with bitcells arranged in columns and rows. The circuitry includes bitlines coupled to the columns of the bitcells and wordlines coupled to the rows of the bitcells. The bitcells are arranged in multiple groups of bitcells along corresponding wordlines in each row, and each group of bitcells in each row is configured to be shifted by at least one column with respect to another group of bitcells in a previous row.