Dynamic Write Driver Logic for Memory Array Power Optimization
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Solution Overview
Problem
The implementation of high-density memory technologies faces challenges in reducing costs and optimizing charge pump circuitry area, as write throughput is dominated by charge pump capability, leading to design trade-offs between cost and area consumption.
Innovation Solution
The introduction of write logic that dynamically assigns permissible numbers of write drivers to apply pulses in parallel, enabling efficient power usage and higher throughput by flagging subsets of bit lines based on data patterns and using mask logic to disable unnecessary drivers, allowing iterative write sequences with varying pulse magnitudes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If charge pump circuitry is designed to support writing large numbers of memory cells in parallel, then write throughput is improved, but area consumption and cost increase
Solution Approach 1:
The patent implements dynamic control of the number of write drivers enabled based on data pattern analysis. The system determines the actual number of memory cells requiring write operations and dynamically adjusts the permissible number of write drivers accordingly, rather than always enabling all N write drivers. This dynamic adaptation allows the charge pump to operate at lower power levels when fewer cells need writing, reducing the required charge pump size and area while maintaining high throughput capability when needed.
Solution Approach 2:
The system changes the operational parameters of the write operation by varying the number of enabled write drivers based on the data pattern. The write logic determines a permissible number of write drivers that is dynamically adjusted according to the actual write requirements, allowing the charge pump to operate with optimized current and voltage parameters for each specific operation, thereby reducing overall area requirements.
2Reliability
If high magnitude write pulses are applied to memory cells, then write operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by enabling only the necessary number of write drivers based on the actual data pattern requirements. Instead of applying high magnitude pulses to all N memory cells simultaneously, the system determines the exact number of cells requiring writes and enables only that many write drivers with high magnitude pulses, while leaving other drivers disabled. This partial application of high-power pulses reduces overall power consumption while maintaining write reliability for the cells that actually need it.
3Productivity
If the number of write drivers enabled is increased, then write throughput is improved, but power consumption and charge pump requirements increase
Solution Approach 1:
The system dynamically adjusts the number of enabled write drivers based on the actual write requirements determined from the data pattern. The write logic analyzes which memory cells need writing and enables only the necessary number of write drivers, optimizing the balance between throughput and power consumption for each specific operation rather than using a fixed high number of drivers.
Solution Approach 2:
The patent changes the operational parameter of the number of enabled write drivers dynamically. By adjusting this parameter based on the actual data pattern and write requirements, the system achieves high throughput when necessary while reducing peak power consumption when fewer cells need writing, eliminating the need for oversized charge pump circuitry.
Data Source
AI summary
For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.