Memory Controller Signal Calibration for Timing Margin
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Solution Overview
Problem
Calibrating the timing margin of the clock enable signal in memory systems is challenging due to the difficulty in measuring it when the memory is switched to a low power status after receiving a power-down or self-refresh command.
Innovation Solution
A signal calibration method that involves generating an under-test signal by the memory controller, issuing a low-power status control command to switch the memory unit to a low power status, and using a read command to determine if the signal phase is within the timing margin by comparing responded data with predetermined data, allowing for iterative adjustments to accurately calibrate the signal phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a power-down command or self-refresh command is issued to switch the memory to low power status, then power consumption is reduced, but the ability to measure timing margin of the clock enable signal is lost
Solution Approach 1:
The patent performs timing margin measurement before issuing the power-down command. The clock enable signal phase is calibrated while the memory is in normal operation mode, allowing accurate measurement of timing margins. Only after the timing margin is confirmed to be within the required range does the system issue the power-down command to reduce power consumption.
Solution Approach 2:
The patent implements a feedback mechanism where the timing margin measurement result is used to control the phase of the clock enable signal. The system continuously monitors the timing margin and adjusts the clock enable signal phase accordingly, ensuring that power-down operations only occur when timing margins are adequate, thus maintaining both low power consumption and measurement capability.
2Use of energy by moving object
If the clock enable signal phase is calibrated by measuring timing margin after power-down command, then power consumption is reduced, but measurement accuracy deteriorates due to low power status
Solution Approach 1:
The patent performs timing margin measurement and clock enable signal phase calibration before the memory enters low power status. By conducting all necessary measurements while the memory is in normal operation mode with stable power supply, the system ensures high measurement accuracy without compromising power savings.
Solution Approach 2:
The patent maintains continuous monitoring and adjustment of the clock enable signal phase during normal operation to ensure timing margins remain within acceptable ranges. This continuous calibration approach allows the system to transition to low power mode confidently, knowing that timing margins are maintained, thus achieving both measurement accuracy and power efficiency.
Data Source
AI summary
A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.