Bus Inversion Decoding for Semiconductor Memory Address Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed semiconductor memory devices face increased power consumption and potential operation speed degradation due to higher address signal input rates, particularly when applying the bus inversion scheme, which can lead to slower data reading and writing operations.
Innovation Solution
A semiconductor memory device incorporating a bus inversion decoding block and an address buffer block that aligns and transfers address signals or their inverted versions based on an indication control signal, ensuring setup/hold times and operation stability by generating a pulse to maintain operation margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the address signal input rate is increased to achieve higher operating speed, then the data input/output speed is improved, but the power consumption increases due to increased voltage toggling
Solution Approach 1:
The patent applies bus inversion scheme where the address signal is inverted (complemented) before being input to the memory device. By transmitting the inverse of the address signal, the number of transitions is reduced when consecutive addresses differ by only one bit, thereby reducing power consumption while maintaining high input rates
Solution Approach 2:
The patent changes the parameter of the address signal by applying inversion transformation. The address bus inverter modifies the signal characteristics by complementing the input address signals, which alters the transition patterns and reduces the frequency of voltage toggling at the input ports
2Speed
If the address signal input rate is increased to achieve higher operating speed, then the data input/output speed is improved, but the setup/hold time may be degraded affecting operation stability
Solution Approach 1:
The address bus inverter performs preliminary inversion of the address signals before they are latched by the input buffer. This preliminary action ensures that the inverted signals are ready and stable before the latching operation, maintaining proper setup and hold times even at high input rates
Solution Approach 2:
The address bus inverter acts as an intermediary component between the external address source and the internal latching circuitry. It buffers and conditions the inverted address signals, ensuring signal integrity and proper timing relationships are maintained throughout the signal path
3Use of energy by moving object
If the bus inversion scheme is applied to reduce power consumption, then the voltage toggling is reduced, but the operation speed may be degraded due to additional signal processing
Solution Approach 1:
The address bus inverter is merged with the address input path and operates in parallel with the main data path. The inversion operation is performed concurrently with other address processing operations, so the additional processing does not create sequential delays that would reduce operation speed
Data Source
AI summary
A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.