DRAM Sampling Timing Generator for Row Hammer Mitigation
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face bit errors due to Row Hammer and Ras-Clobber effects, which existing auto-refresh mechanisms fail to prevent effectively, leading to data loss in adjacent memory cells.
Innovation Solution
A semiconductor device with a sampling timing generator circuit and sampling circuits that dynamically control steal-refresh operations by randomizing the timing of row address sampling, using a self-refresh oscillator to generate a frequency-divided oscillation signal for randomized ArmSample signals, and a multiplexer to select between row and adjacent addresses for refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time-based random sampling of row address is used to control steal-refresh operations, then bit errors due to Row Hammer and Ras-Clobber effects are reduced, but empty-hits occur when there is no memory access due to absence of active commands
Solution Approach 1:
The patent makes the refresh operation dynamic by transitioning from fixed periodic refresh to event-driven refresh. The sampling timing generator dynamically adjusts refresh timing based on detected active commands, making the system adaptive to actual memory access patterns rather than following a rigid schedule.
Solution Approach 2:
The patent implements feedback by detecting active commands and using this information to trigger refresh operations. The sampling timing generator monitors memory access commands and adjusts refresh timing based on this feedback, creating a closed-loop system that responds to actual system conditions.
2Reliability
If auto-refresh commands are issued periodically at fixed frequency, then all word lines are refreshed within one refresh cycle, but refresh operations cannot prevent bit errors due to Row Hammer and Ras-Clobber effects
Solution Approach 1:
The patent transforms the static, periodic refresh schedule into a dynamic, event-driven refresh mechanism. Instead of refreshing at fixed intervals regardless of activity, the system dynamically triggers refresh operations based on detected active commands, adapting to actual memory usage patterns.
Solution Approach 2:
The patent changes the timing parameter of refresh operations from fixed periodic intervals to variable event-driven intervals. The sampling timing generator modifies refresh timing parameters based on detected command patterns, allowing the system to adapt refresh frequency to actual memory access behavior.
3Reliability
If steal-refresh operations are carried out to refresh memory cells coupled to non-selected word lines, then bit errors due to Row Hammer and Ras-Clobber effects are prevented, but system complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory system to autonomously detect active commands and trigger appropriate refresh operations without external intervention. The sampling timing generator automatically monitors commands and initiates steal-refresh operations based on detected patterns, reducing the need for complex external control logic.
Solution Approach 2:
The patent merges the command detection function with the refresh control function in the sampling timing generator. By combining these previously separate functions into a single integrated unit, the system reduces overall complexity while maintaining the ability to perform targeted refresh operations.
Data Source
AI summary
Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.