Conductive Cap Wrapping Memory Pillar for Metal Line Integration
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Solution Overview
Problem
The integration of memory devices like MRAM, PCM, and RRAM into advanced logic nodes is challenging due to the narrow separation between metal lines, which is smaller than the minimum pillar height, and conventional methods struggle to achieve this without risking shorts or over-etching of sidewall spacers.
Innovation Solution
A memory device design featuring a conductive cap wider than the memory pillar, which wraps around the sidewall spacers and memory stack, using a metal-on-metal deposition method to form a mushroom-shaped cap, and an etch-selective metal cap to prevent spacer erosion and allow the top metal line to wrap around the encapsulated memory stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form metal lines over memory pillars, then the manufacturing process is simpler, but the separation between metal lines becomes too narrow, risking shorts and over-etching of sidewall spacers
Solution Approach 1:
A conductive cap is introduced as an intermediary element between the memory pillar and the upper metal line. This cap extends beyond the sidewall spacer to provide a protective barrier during etching processes, preventing spacer erosion while enabling the metal line to wrap around the memory stack with sufficient separation to avoid shorts.
Solution Approach 2:
The conductive cap is formed in advance before the upper metal line deposition. This preliminary action ensures that the spacer is protected from over-etching during subsequent processing steps, and the cap's extended structure is already in place to guide the metal line wrapping process with proper spacing.
2Productivity
If the top metal line wraps around the memory stack, then integration density is improved, but the risk of shorts between metal line and memory layer increases
Solution Approach 1:
The conductive cap serves as a mediator that physically separates the upper metal line from the memory layer during the wrapping process. By extending beyond the sidewall spacer, it creates a reliable isolation barrier that prevents direct contact and potential shorts while still allowing the metal line to wrap around for high integration density.
3Manufacturing precision
If etching is performed to form metal line trenches, then metal lines can be positioned, but sidewall spacers may be over-etched and eroded
Solution Approach 1:
The conductive cap is formed beforehand to cushion and protect the sidewall spacer during etching processes. The cap extends beyond the spacer to absorb the etching attack, preventing spacer erosion while still allowing precise metal line positioning through the etched trenches.
Solution Approach 2:
The conductive cap acts as an intermediary protective layer between the etching process and the sidewall spacer. It absorbs the harmful etching effects that would otherwise damage the spacer, enabling precise metal line positioning without compromising spacer integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the risk of shorts between the overlying metal line and the memory layer, prevents spacer erosion, and enables the top metal line to wrap around the memory stack effectively, facilitating the integration of memory devices in logic devices as standalone or dynamic memory.
Implementation Method 1
the sidewall spacer and conductive cap physically separates the upper metal line from the memory stack
Implementation Method 2
using a metal-on-metal deposition method to form a mushroom-shaped cap
Implementation Method 3
using a metal-on-metal deposition method to form a mushroom-shaped cap, and an etch-selective metal cap to prevent spacer erosion
Data Source
AI summary
A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.