Semiconductor Device Delay Selection Signal Generation Circuit
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Solution Overview
Problem
As data transmission speeds in semiconductor devices increase, so does the probability of errors, necessitating effective error correction mechanisms to maintain reliability, particularly in DDR2 and DDR3 schemes.
Innovation Solution
A semiconductor device incorporating a delay selection signal generation circuit, internal read and write signal generation circuits, and a data storage circuit that performs a data scrub operation by generating delay selection signals and delaying mask write signals to enable internal read and write signals, allowing for error correction and data storage, thereby stabilizing the data scrub operation across varying clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve productivity, then the probability of errors in data transmission increases, worsening reliability
Solution Approach 1:
The patent implements preliminary error correction by performing scrub operations on data before it is read from the memory device. The controller detects and corrects errors in advance using ECC codes, so that when data is subsequently read at high speeds, the errors have already been corrected, maintaining reliability while enabling high productivity
2Reliability
If error correction codes are added to improve reliability, then device complexity increases
Solution Approach 1:
The memory device performs self-correction of errors through integrated ECC circuits within the memory device itself. The scrub operation automatically detects and corrects errors without requiring external intervention, making the system self-sufficient in maintaining data integrity while minimizing additional complexity
Solution Approach 2:
The error correction functionality is merged with the existing memory control logic. The controller integrates ECC encoding, decoding, and scrub operation control into its existing architecture, combining multiple functions into a unified control structure that reduces overall system complexity
3Device complexity
If delay periods are fixed to simplify control, then the data scrub operation cannot adapt to varying clock frequencies, worsening adaptability
Solution Approach 1:
The delay periods in the control signal generation circuits are made dynamic rather than fixed. The delay selection signal generation circuit selectively adjusts delay periods based on detected clock frequency, allowing the system to adapt to different operating speeds while maintaining proper timing relationships for scrub operations
4Reliability
If delay periods are extended to ensure sufficient error correction time, then productivity decreases
Solution Approach 1:
Error correction is performed in advance during scrub operations before data is read. This preliminary correction ensures that when data is subsequently read at high speeds, the correction process does not need to extend the delay periods, as errors have already been corrected in the background
Data Source
AI summary
A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.