Semiconductor Decoder Segmentation for Operation Margin
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving a high operation margin, which is essential for efficient data storage and access.
Innovation Solution
A semiconductor device comprising a memory cell array, a voltage generator, and a decoder section, where the memory cell array has first and second selection lines, and the decoder section includes selection transistors and a gate driving section to apply a selection voltage and a driving voltage, respectively, to select memory cells and enhance operation margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional decoder section with selection transistors is used to select memory cells, then the device can operate, but the operation margin is insufficient
Solution Approach 1:
The decoder section is divided into a first decoder for selecting first selection lines and a second decoder for selecting second selection lines. This segmentation allows independent optimization of each decoder, enabling the application of different driving voltages to different transistor groups, thereby improving the operation margin without requiring a complete redesign of the entire decoder structure.
Solution Approach 2:
Different driving voltages are applied to different groups of transistors based on their specific functional requirements. The first decoder uses a first driving voltage for its transistors while the second decoder uses a second driving voltage for its transistors. This local differentiation of electrical characteristics optimizes the switching performance and operation margin for each selection line group independently.
2Quantity of substance
If the number of selection lines is increased to expand memory capacity, then the storage capacity improves, but the complexity of voltage control and selection increases
Solution Approach 1:
The memory cell array is divided into multiple blocks with separate first and second decoders for each block. This segmentation enables parallel decoding operations, where each decoder independently manages a subset of selection lines, thereby scaling memory capacity without proportionally increasing the complexity of voltage control logic in a single decoder.
Solution Approach 2:
The selection process transitions from a single-dimension decoder to a two-dimension decoder system with first decoders and second decoders operating independently. This dimensional expansion allows the system to manage a larger number of selection lines by distributing the control across multiple decoder units, effectively scaling memory capacity while managing control complexity through modular architecture.
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes: a memory cell array including a plurality of first selection lines extending in a first direction, a plurality of second selection lines extending in a second direction, and a plurality of memory cells each provided between the plurality of first selection lines and the plurality of second selection lines; a voltage generator that is configured to generate a selection voltage to be applied to one of the plurality of first selection lines; and a decoder section that includes a plurality of selection transistors and a gate driving section, and selects one of the plurality of first selection lines and applies the selection voltage to the selected first selection line, the plurality of selection transistors each provided in a plurality of selection paths coupling the plurality of first selection lines and the voltage generator, the gate driving section that drives gates of the plurality of transistors and is configured to apply a first driving voltage to the gates of the plurality of transistors, the first driving voltage being a positive voltage exceeding a withstand voltage of the plurality of selection transistors.