Write-Assist Column for SRAM Write Voltage Reduction
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Solution Overview
Problem
Current SRAM arrays face challenges in reducing write voltage while maintaining write-ability and reliability, as lowering the minimum write voltage reduces headroom and increases memory errors due to limitations in transistor threshold voltage reduction.
Innovation Solution
A write-assist column comprising multiple write-assist cells with pull-up and pass-gate transistors, controlled by signals to adjust the voltage array from a system voltage to a lower predetermined write voltage, enhancing write operation efficiency and reducing memory errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the minimum write voltage (Vmin) is reduced to lower power usage and improve efficiency, then power consumption decreases, but write-ability of the SRAM cell decreases due to insufficient headroom between input voltage and transistor threshold voltage
Solution Approach 1:
A write-assist column is introduced as an intermediary component between the standard SRAM array and the write operation control logic. This write-assist column includes specialized cells with modified transistor configurations that generate assist signals to enhance the write operation. The write-assist column acts as a mediator that provides the necessary voltage boosting and signal conditioning to enable reliable writes at reduced Vmin, thus resolving the contradiction between low power consumption and maintained write-ability
Solution Approach 2:
The invention modifies the voltage parameters dynamically during write operations. By reducing the minimum write voltage (Vmin) while using the write-assist column to provide localized voltage boosting through modified transistor configurations, the system changes the operating voltage parameters to achieve both lower power consumption and maintained write-ability. The write-assist column enables the system to operate at lower voltages while compensating for the reduced headroom through controlled parameter changes in the assist circuitry
2Reliability
If write assist techniques use negative bit-line voltage to improve write-ability, then write-ability improves, but the voltage rapidly dissipates due to high resistance on the bit-line
Solution Approach 1:
The invention extracts the voltage boosting function from the main SRAM array and places it in a separate write-assist column. By removing the complex negative voltage generation and maintenance logic from the core array, the system avoids the high resistance dissipation problem on the bit-line. The write-assist column uses dedicated transistors with modified configurations to generate assist signals that are more stable and have longer duration, resolving the contradiction between improved write-ability and sustained voltage duration
3Reliability
If the strength of PMOS in latch portion is decreased to improve write-ability, then write-ability improves, but memory errors increase and reliability decreases
Solution Approach 1:
The invention segments the SRAM structure into standard array cells and a separate write-assist column with modified cells. The write-assist column contains cells with decreased PMOS strength that generate assist signals, while the main array cells maintain their original, more reliable PMOS configurations. This segmentation allows the system to exploit the write-ability benefits of weaker PMOS in the assist column without introducing memory errors in the main storage array, thus resolving the contradiction between improved write-ability and reduced memory errors
Data Source
AI summary
A write-assist cell includes a first pull-up transistor electrically coupled to a voltage array and a first node, a first pass-gate transistor electrically coupled to the first node, and a bit-line electrically coupled to the first pass-gate transistor and a pull-down voltage. The first pass-gate is configured to selectively couple the bit-line to the first node. The pull-down voltage is configured to adjust a voltage of the voltage array from a first voltage to a second voltage when the bit-line is coupled to the first node.