2T0C Memory Cell With Vertical Gate Transistor
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Solution Overview
Problem
Current Dynamic Random Access Memory (DRAM) memory cell structures face challenges with high power consumption due to capacitor leakage and large area occupation, making miniaturization difficult.
Innovation Solution
A 2T0C memory cell design featuring a read transistor and a write transistor with a horizontal channel, where the second transistor's gate is vertically oriented and not stacked with the first transistor, allowing for a compact structure and simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used to store data in a 1T1C memory cell structure, then data storage capability is achieved, but power consumption increases due to capacitor leakage and refresh requirements
Solution Approach 1:
The patent removes the capacitor component from the memory cell structure, transitioning from a 1T1C (one transistor, one capacitor) design to a 2T0C (two transistors, zero capacitors) design. The capacitor's data storage function is replaced by using the gate capacitance of transistors and changing transistor transconductance to store information, thereby eliminating the harmful leakage and refresh operations associated with separate capacitors.
Solution Approach 2:
The patent substitutes the electrical storage mechanism (capacitor) with a transistor-based mechanism using gate capacitance and transconductance control. This replacement eliminates the need for separate capacitor structures and their associated leakage problems, achieving data storage through transistor electrical characteristics rather than dedicated capacitive elements.
2Reliability
If a capacitor is used in the memory cell structure, then data storage is enabled, but the manufacturing area increases making miniaturization difficult
Solution Approach 1:
The patent extracts and removes the capacitor element from the memory cell structure, replacing it with transistor-based storage mechanisms. This elimination of the separate capacitor component directly reduces the area occupied by the memory cell, enabling further miniaturization while maintaining data storage functionality through gate capacitance and transconductance control.
3Productivity
If transistors are arranged in a stacked configuration, then vertical integration is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the transistor structures by orienting the second transistor's gate vertically while keeping the first transistor's gate horizontal, allowing them to be manufactured using separate, simplified processes rather than requiring complex integrated stacking. This segmentation enables independent optimization of each transistor's fabrication while achieving vertical integration in the final structure.
Solution Approach 2:
Instead of stacking both transistors vertically (which would increase manufacturing complexity), the patent inverts the approach by making the second transistor's gate vertical while keeping the first transistor's gate horizontal. This inversion allows for simpler manufacturing processes while still achieving the desired vertical integration and compact form factor.
Data Source
AI summary
A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.